10cx220YU484的2A-bank上驱动两个trible speed ethernet。

[smile123]

现在我在10cx220YU484的2A-bank上驱动两个trible speed ethernet，IP核是only pcs，引脚为lvds-io，使用2A-bank的专用时钟引脚输入参考时钟，例化了两个trible speed ethernet模块，但是编译显示，内部PLL使用冲突，是不是同一个BANK只能例化一个trible speed ethernet模块？

[Deshi_Intel]

HI,

Unfortunately that's the case.

TSE IP don't support PLL merging feature unless you configure multi channel in TSE IP but I recalled multichannel support is only for 4 channel and not 2 channel

Thanks.

Regards,

dlim

[smile123]

很感谢您的回答，我在IP核里面并没有找到支持4通道的配置选项。请问可以给予具体的信息吗？

[Deshi_Intel]

Attached is TSE multi port selection explanation

[Deshi_Intel]

HI,

Sorry, I took a deeper look. TSE multiport selection is only available in TSE MAC IP and not on PCS IP

My previous post show you the TSE IP screenshot explanation.

So, looks like you can only use one TSE IP per one IO bank

Regards,

dlim