FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5151 Discussions

10cx220YU484的2A-bank上驱动两个trible speed ethernet。

smile123
Novice
304 Views

现在我在10cx220YU484的2A-bank上驱动两个trible speed ethernet,IP核是only pcs,引脚为lvds-io,使用2A-bank的专用时钟引脚输入参考时钟,例化了两个trible speed ethernet模块,但是编译显示,内部PLL使用冲突,是不是同一个BANK只能例化一个trible speed ethernet模块?

0 Kudos
4 Replies
Deshi_Intel
Moderator
294 Views

HI,


Unfortunately that's the case.


TSE IP don't support PLL merging feature unless you configure multi channel in TSE IP but I recalled multichannel support is only for 4 channel and not 2 channel


Thanks.


Regards,

dlim




smile123
Novice
283 Views

很感谢您的回答,我在IP核里面并没有找到支持4通道的配置选项。请问可以给予具体的信息吗?

Deshi_Intel
Moderator
280 Views

Attached is TSE multi port selection explanation

Deshi_Intel
Moderator
280 Views

HI,


Sorry, I took a deeper look. TSE multiport selection is only available in TSE MAC IP and not on PCS IP


My previous post show you the TSE IP screenshot explanation.


So, looks like you can only use one TSE IP per one IO bank


Regards,

dlim


Reply