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1G/10GbE IP works on 1G/10G mode with auto-negotiation turned off

Hi,

Could you help to give some advices?

 

There are two 1G/10GbE phys with 1G/10G and RX+TX mode in A10GX, connected with only one fiber, that is: one PHY works on TX only, and the other one works on RX only.(although the configuration is RX+TX mode.)

 

The config register with base address 0x400 is 8, auto-negotiation is turned off. PHYs work on 1Gbps.

 

It works rightly when download sof with fiber module plugged in. the led_link and led_an all pull high and the data received correctly.

 

But after pull out and re plug in the fiber module, the led_link is pulled high, but the led_an remains low. Then customer reset the PHY reset IP, it makes no change. led_link is 1, led_an is 0. and no data is received, while data is observed been transmitted on GMII interface on the TX channel of the other PHY.

why led_an remains low after re plugged with auto-negotiation is off? why there is no data received with led_link up? but only can received correctly when led_an is up?

Thanks!

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Hi,

 

As I understand it, you are observing no output data from the RX after you unplug and plug back the fiber in C10GX devices using the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core. The AN feature is turned OFF in the PHY. 

 

To ensure we are on the same page, just would like to check with you on the following:

 

1. Just would like to check with you on the specific Quartus version that you are using?

 

2. I understand that you have two duplex PHY IP instances with one PHY A TX sending data to PHY B RX. Would you mind to try using one duplex PHY IP and then perform a fiber loop from TX back to its own RX to see if similar issue occurs? This would help to facilitate and ease further debugging.

 

3. As I understand it, the register 0x400 has value of 0x8. The link is operating at 1G without AN. Just wonder if you have had a chance to monitor register 0x400 before cable unplug, after cable unplug and after cable replug to see if there is any difference.

 

4. I understand that you mentioned triggering reset does not recover the PHY. Would you mind to further elaborate which specific reset are you referring to? Just wonder if you are triggering reset to the PHY IP as well as the XCVR reset controller?

 

5. Would you mind to help tapping status signals ie rx_is_lockedtodata, tx_cal_busy and rx_cal_busy to check on the CDR and calibration?

 

6. Mind sharing me with the .ip file of you PHY so that I can have better understanding of your configuration.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

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Hi Chee, Thanks so much for your kindly reply. 1. Just would like to check with you on the specific Quartus version that you are using? A: I will check with customer later. 2. I understand that you have two duplex PHY IP instances with one PHY A TX sending data to PHY B RX. Would you mind to try using one duplex PHY IP and then perform a fiber loop from TX back to its own RX to see if similar issue occurs? This would help to facilitate and ease further debugging. A: one duplex PHY with fiber loop back can receive correctly after unplug and plug back the fiber. 3. As I understand it, the register 0x400 has value of 0x8. The link is operating at 1G without AN. Just wonder if you have had a chance to monitor register 0x400 before cable unplug, after cable unplug and after cable replug to see if there is any difference. A: sure, will do the experiment later. 4. I understand that you mentioned triggering reset does not recover the PHY. Would you mind to further elaborate which specific reset are you referring to? Just wonder if you are triggering reset to the PHY IP as well as the XCVR reset controller? A: I meant the altera transceiver PHY reset controller IP, with default preset(rx_analogreset duration 70000ns, rx_digitalreset duration 4000ns ) 5. Would you mind to help tapping status signals ie rx_is_lockedtodata, tx_cal_busy and rx_cal_busy to check on the CDR and calibration? A: check the LTD and LTR. The CSR address 0X464H is all FFs. 6. Mind sharing me with the .ip file of you PHY so that I can have better understanding of your configuration. A: I will check with customer. Regards, Nicole
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Hi Chee Sorry I made a mistake, the PHY IP is 1G/10GbE and 10Gbase-KR phy on A10GX. But other describtion are correct. Q17.1.2Pro. The PHY file is as attached. Regards, Nicole
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Hi Nicole,

 

Thanks for your clarification that our customer is using the 1G/10G in 1G/10GbE and 10Gbase-KR PHY IP core.

 

Please see my comments as following:

 

1. check the LTD and LTR. The CSR address 0X464H is all FFs.

[CP] As I understand it from the user guide, the 0x464 for 1G/10G PHY is referring to pma_rx_set_locktoda

ta. Can you help to check on 0x466 (pma_rx_is_lockedtodata) and 0x467 (pma_rx_is_lockedtoref) to see if the CDR is in LTD or LTR mode.

 

2. With reference to the 0x400 register, as I understand it, the 1G/10G PHY seems does not support this register. Just wonder if our customer is referring to other register?

 

By the way, I notice that you have open another Forum case 4591444 in which the TX seems to have no output. Not sure if the TX no output issue is causing the RX issue that we are seeing in this case? Or if there are separate issues.

 

Please let me know if there is any concern. Thank you.

 

 

Best regards,

Chee Pin

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Hi Chee, Thanks. We will try. These two issues are all in the same project, but not related. This issue is caused by fiber re plug. That issue is caused by recompilation. Thanks for all your supports! Regards, Nicole
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Thanks lot. By the way, would you mind to share the .qsys file of your 1G/10G IP? I seems could not locate in the case. Thank you. Best regards, Chee Pin
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HI Chee Pls see the IP on attached. Thanks! Regards, Nicole
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Hi Nicole,

 

Thanks for your help and clarification. I have dropped you an email regarding the attachment.

 

Also, please feel free to keep me posted on the finding to my previous inquiries when there is any update.

 

Thank you.

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