Has anyone successfully gotten the physical on the cyclone III demo board to work with the RMGII interface? After looking at all of the documentation for the kits for Altera, none of them use the interface for 1GE, they are 100Mbit.I can get the kit to work, but it is intermittent, which points me to the SDC file. So if you have it working, please tell me what you used for the min/max delays and clock. Thanks
The standard nios reference design delivered with the kit is using the PHY chip with a RGMII interface at 1gigabit. IIRC they didn't bother to put SDC constraints and the interface is just working out of pure luck.Are you using the Altera drivers with the Interniche stack? There is a register in the PHY chip to shift the RGMII signals by 90 degres, which can help in some situations. I think the driver does that during setup.
Those are the sdc files from the linux example design, you should be able to copy/paste them in your own.Alternatively I wrote this message (http://www.alteraforum.com/forum/showpost.php?p=11013&postcount=4) a while ago with the settings I used, but I haven't done anything with Marvell PHYs in a while...
:-PThanks for the post on the SDC files. I wanted to let you know that it turned out to be our fault in the design. It appears that high speed serial inputs should not really be considered synchronous. Our state machine reading in the data at the MAC layer was going into an unknown state. We are using additional DFF's to sync the input data, and using the setting in Altera synthesis for safe state machine recovery. When I have time I will go back and fix the state machine by manually defining all states and the transitions.
hi Daixiwen can u send me setup of working rgmii in 1gmode using tse with sdcas soon as possible the tse is time consuming process and i cant wait for still more time,help me to bring up the rgmii in 1g mode revert for any clarifications