The customer need 20 10GE in Stratix 10 MX 1SM16B, we use the 10GE low latency 10GE MAC example design. we found it has the parameter NUM_CHANNELS in hdl code
the parameter NUM_CHANNELS would be from 1 to 12. but when we change the parameter NUM_CHANNELS above 6. it would fail.
I found the ATX PLL would be limited for this design. how we do for 12 channels?
In general, you can check out all Ethernet IP solution supported by Intel FPGA in below link.
As you can see from above link - Etile Ethernet IP is called "E-Tile Hard IP for Ethernet"
- One IP can be configured to support max till 4 channels.
- Also, just curious why does customer wants to use Etile if customer is just targeting 10G application while Etile is meant to support till 56G ?
And also to address your concern better, Intel also developed an excel tool called Ethernet pin placement tool to guide user on how to fit IP solution into one Etile. Different setting selection like RSFEC and PTP will affect Etile pin placement accordingly.
- You can download Etile pin placement tool from below link -> Design flow and IP integration -> Etile channel placement tool
Can you tried out the Etile pin placement excel tool first as I mentioned in my previous reply ?
- Don't worry about Quartus design for now as your concern is how to fit 20+ 10GE with one E tile, right ?
- Different Ethernet setting like RSFEC and PTP may affect the pin placement result also
Once you have verified customer Ethernet design setting requirement is able to fit into one Etile, then only you start look into creating multiple Etile hard IP in Quartus project to estimate the resource.
I have not hear back from you for close to 2 months.
Hopefully you find Etile pin placement tool useful.
For now, I am setting this case to closure.