FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5892 Discussions

2pcs EP2SGX60EF1152C4 were found J05 open to GND issue at flex

WXu001
Beginner
700 Views
 
0 Kudos
6 Replies
Zawani_M_Intel
Employee
434 Views

Hi WXu001,

 

Deeply apologize for my delay in respond as the case just been assigned to me.

To help me to understand more on your issue, can you provide me some details :

 

1. What is the failure symptom? Please elaborate the failure symptom in detail. 

2. When did the failure happen? How did you discover the failure? 

3. How did you determine the failure? Please elaborate the procedures. 

4. Does the failure unit ever working before failure?

5. Did they violate solder re-flow temperature profiles, moisture sensitivity? Please provide the re-flow temperature profiles. 

6. Did you swap the failure device to a known good board? Is the failure following the device or board?

 

Please do not share confidential info publicly. If you need to send any confidential info or document, please send it privately.

 

Thanks!

 

Regards,

Wani

0 Kudos
WXu001
Beginner
434 Views

Hi Wanni,

 

Please see my answers below, thanks.

1.What is the failure symptom? Please elaborate the failure symptom in detail. 

 

    Two pieces of EP2SGX60EF1152C4 were on two BIB boards tested function , failed “eeprom” , sent two BIB boards to ICT test , found 2pcs BGA point J05 open to GND .

2. When did the failure happen? How did you discover the failure? 

Failure happened in the middle of April , found BGA point J05 open to GND in the middle of June.

Firstly tested function , failed “eeprom” .

Secondly sent two BIB boards to ICT test , found 2pcs BGA point J05 open to GND

Thirdly removed the 2pcs BGA from the BIB boards , measure 2pcs BIB boards with a multimeter , didn’t find trace or via hole open . Then added new BGA on BIB boards tested pass.

      Last , measure 2pcs BGA with a multimeter , found point J05 open to GND , normal known good should be 300+ Ohm.

 

3. How did you determine the failure? Please elaborate the procedures. 

 

First tested function , failed “eeprom” .

 Second sent two BIB boards to ICT test , found 2pcs BGA point J05 open to GND .

 Third removed the 2pcs BGA from the BIB boards , measure 2pcs BIB boards with a multimeter , didn’t find trace or via hole open . Then added new BGA on BIB boards tested pass.

Last , measure 2pcs BGA with a multimeter , found point J05 open to GND , normal known good should be 300+ Ohm.

4. Does the failure unit ever working before failure?

   No , function test failed when the first time.

5. Did they violate solder re-flow temperature profiles, moisture sensitivity? Please provide the re-flow temperature profiles. 

    I'm collecting this information from our PE, will provide to you later.

 

6. Did you swap the failure device to a known good board? Is the failure following the device or board?

   We didn’t do swap . We have measured the BGA , the failure following the BGA .

0 Kudos
Zawani_M_Intel
Employee
434 Views

Hi WXu001,

 

Are you referring J05 to J5?

Please share the re-flow temperature profile once available then we will proceed with shipping instruction if required (Do not share any private document publicly).

 

Thanks!

Wani

0 Kudos
WXu001
Beginner
434 Views

​Hi Wani,

 

J05 and J5 are the same,  J05 open to GND, one GND is A02.

Please see the profile as attached, thanks.

0 Kudos
Zawani_M_Intel
Employee
434 Views

Hi WXu001,

 

I approve your ERMA request. I will provide shipping instruction via private message. Please do let me know if you not receive it.

 

Thanks!

Wani

0 Kudos
Deshi_Intel
Moderator
434 Views

Hi WXu001,

 

I am setting this case to closure as final FA report has been provided to you by private message.

 

Thanks.

 

Regards,

dlim

 

 

0 Kudos
Reply