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Novice
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4-bit Synchronous JK flip flop Counter Erratic

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See attached image. Built a simple 4-bit synchronous counter in Quartus Prime using 7473 chips.

This works erratically on DE10-Lite board with standard MAX 10 FPGA.

Expect synchronous counting, but it sometimes counts 1-2-3 and then either won't increment further even with additional clock pulses or else it does some seemingly random counting.

No better with single-chip JK FFs in Quartus.

Slightly better with output current adjusted down to 8 mA and slew rate set to minimum setting of arbitrary "0".

Works FINE with 7490 counter chip instead of JKs.

Am I missing something simple like propagation delay?

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Moderator
116 Views

It's very important to learn how to create timing constraints for an FPGA design. Start with this online training:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

 

For simulation, this should help:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/ouwsdbug.html

 

#iwork4intel

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7 Replies
Novice
116 Views

BTW, the 7490 chip is asynchronous.

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Moderator
116 Views

What's your clock speed? What does your .sdc file look like?

 

#iwork4intel

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Novice
116 Views

Thank you for responding.

I believe the default clock speed for this board is 50 MHz and I've done nothing to change it. If you're asking about the SIMCLK input, that's a pushbutton on the DE10-Lite board that we're clocking very, very slowly.

I have no .sdc file in the project.

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Moderator
116 Views

You should try simulating the design with the included ModelSim-Intel FPGA starter edition software. Also, you should add a .sdc file. Without that, there's no guarantee that the Fitter will place and route your design in such a way to meet timing.

 

#iwork4intel

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Novice
116 Views

Thank you for your additional response. I'm not a total beginner to Quartus, but my experience has been with a much older version (Quartus II). So, pretend I'm a beginner and that will pretty well be true.

Spent some time running ModelSim as a separate tool to follow up on your suggestion, but the 500+ page manual was a bit daunting. The 80-page tutorial from Intel was not much more friendly. Then I found a random web post suggesting that ModelSim not be run as a separate tool but integrated into a Quartus project by selecting it as an EDA tool when creating a new project. Tried it and it launched ModelSim at end of compile, but still not quite there yet. Any suggestions on a good tutorial to get a quick start on using Quartus Prime Lite with ModelSim for the MAX 10 FPGAs?

Also, can you please help me understand how to create an sdc file and determine what the contents should be? It doesn't seem to be generated by ModelSim; I found one example in the DE10-Lite docs and it says the following:

# This .sdc file is created by Terasic Tool.

# Users are recommended to modify this file to match users logic.

 

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Moderator
117 Views

It's very important to learn how to create timing constraints for an FPGA design. Start with this online training:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

 

For simulation, this should help:

 

https://www.intel.com/content/www/us/en/programmable/support/training/course/ouwsdbug.html

 

#iwork4intel

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Novice
116 Views

Great resources. I've watched the first training slide show and already have a better understanding of SDC file contents and timing constraints. Thank you so much!

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