FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

50/60Hz Digital PLL

hpola3
Beginner
266 Views

We want to implement a digital 50/60Hz PLL for synchronisation purpose.

We want to replace an old HEF4046B IC.

Is it possible to design a 50/60Hz with FPGA/CPLD (MAX10 family i.e)? do you have any reference design?

0 Kudos
5 Replies
Rahul_S_Intel1
Employee
162 Views

Hi ,

You can use PLL for the generation

Rahul_S_Intel1
Employee
162 Views

Hi ,

Kindly let me know , if you need further assistance.

 

Regards,

Rahul S

hpola3
Beginner
162 Views

Hi Rahus,

 

In Max10 internal PLLs minimum frequency range is in MHz range.

I need a PLL for 50/60Hz application (grid frequency lock). Also PLLs has a filter which adjust its slew rate and speed.

Do you think is it possible with Max10 family? Do you have an IP of reference design for such application?

Rahul_S_Intel1
Employee
162 Views

Hi ,

May I know the below suggestion will work or not .

Implement a counter , where you know the input frequency and make the counter to your desired clock out put . I find my code may be it will be useful for you .

 

library IEEE;

use IEEE.NUMERIC_STD.all;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity scale_clock is

 port (

  clk_50Mhz : in std_logic;

  rst    : in std_logic;

  clk_2Hz  : out std_logic

);

end scale_clock;

 

architecture Behavioral of scale_clock is

 

 signal prescaler : unsigned(23 downto 0);

 signal clk_2Hz_i : std_logic;

begin

 

 gen_clk : process (clk_50Mhz, rst)

 begin -- process gen_clk

  if rst = '1' then

   clk_2Hz_i  <= '0';

   prescaler  <= (others => '0');

  elsif rising_edge(clk_50Mhz) then  -- rising clock edge

   if prescaler = X"BEBC20" then   -- 12 500 000 in hex

    prescaler  <= (others => '0');

    clk_2Hz_i  <= not clk_2Hz_i;

   else

    prescaler <= prescaler + "1";

   end if;

end if;

 end process gen_clk;

 

clk_2Hz <= clk_2Hz_i;

 

end Behavioral;

 

Rahul_S_Intel1
Employee
162 Views

Hi ,

Kindly let me know if you need further assistance

Reply