FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5346 Discussions

A question about Avalon-MM waitrequestAllowance spec.

CHung
Novice
260 Views

Hi​

​Why does master need to hold data for 2 cycles in figure 10?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

Thanks.

0 Kudos
0 Replies
Reply