on our customer A10SOC board, uboot runs firstly w/ SDCard boot mode. After u-boot launch, it will READ FPGA *.rbf File from SDcard, then load it into A10 FPGA fabric. But we see board (SOC console) hangs immediately once the rbf file is loaded , and mesage as below:
U-Boot 2014.10 (Sep 17 2020 - 18:02:02)
CPU : SOCFPGA Arria 10 Platform
BOARD : SOCFPGA Arria 10 Kit
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
FPGA: writing adrv9009_a10soc.rbf ...
My question is : (1) does this mean FPGA had beed re-configured successfully ?
(2) Is that possible FPGA can break SOC side ? Why?
(3) My undrstandng is : FPGA must be re-configed firstly, then SOC DDR4 is able to be initiazied. Is it possbile the SOC DDR can be used, w/o FPGA fabric runs up ?
I'm a bit new to SOC world, thus please give more expert advices. Thanks lot !!!
1) When FPGA is configured successfully, it will prompt something like "FPGA configured successfully" after loading the .rbf
2) Actually, this highly depends on the design on where the FPGA is actually loaded from, and the settings and configuration need to be set correctly. Additionally, there you may set the FPGA to load the full .rbf or loading split .rbf (peripheral and core rbf)
3) I recommend that you read the Arria 10 SoC Boot User Guide first on this,
Also to take note, there is an Early IO release feature for Arria 10 SoC which can be enabled or disabled. More info you can find in below link, if you have more questions regarding it, let me know.