I apologize that I may not understand your question, can you elaborate on what is collecting the 50k samples? and which device are you actually referreing to? Cyclone V SoC, Arria 10 SoC etc.
Hi, thank you for your reply.
i have the ADC-SOC Board from Terasic with a Cyclone V SoC. Terasic provided an example for the two on-board high speed ADC. in this example they store the adc samples in the "on-chip memory".
my question is how can i use the sdram that is connected to the HPS side of the SOC to collect more samples. also what are the limitation of the direct accesses to the sdram when the sample rate is 100MSamples/sec.
Unfortunately, we do not any example design that is related to SDRAM usage for ADC.
However, you may design that the on-chip memory to transfer the data to sdram, but requires a DMA controller, there is an example you may check: