in the compilation report, I don't understand how the number of used combinational gates plays against ALMs.
Originally I had a function that used several +/* on float64 and compiling that (30minutes+) resulted in 50% of utilized ALMs. I then dropped that function and implemented a component (same algorithm) and I noticed that the number of ALMs is now 1/80,330 (<1%). So.. why such a different hardware utilization?
Now looking at the "Hierarchies optimized during sweep" I see that my design is using 50 multiplications and more than 120.000 number of combinational logic gates. Why this "high" number of logic gates does not show up in the ALM utilization? What am I missing?
Quartus Prime Pro 22.2, device family Cyclone 10 GX, see the attached screenshots. I noticed that adding floating point multiplications in my vhdl component reflects in increasing the number of "used combinational gates", but I don't know why in the overall Logic Utilization I see just 1/80,330 <1%.
On the contrary rewriting the vhdl component into a vhdl function, would bump the Logic Utilization from 1/80,330 <1% to something like 50%.
As I understand your query, you are seeing a drastic reduction in utilization of ALMs after changing the code from function to a component.
I suspect that there is something missing in the code and that the logic is being removed. Recommend to review check all the connections to the component in the HDL. To confirm, use the Technology Map Viewer and see if really the logic got implemented or not.