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ALTLVDS_RX inclok pin. Dedicated clock port?

de10
Beginner
244 Views

I'm designing an FPGA, using Enclustra Mercury PE1 and SA2. The FPGA is Cyclone V ST D6.
I'm trying to assign the data entry and clock pins. Someone knows if it is possible to connect the inclock input to any differential I/O. Or do I have to use dedicated clock pins (clk[0..7])?

Attach the image marking the pins dedicated to clk:

 

de10_4-1619440944211.pngde10_0-1619442602135.pngde10_2-1619442661296.pngde10_3-1619442698314.png

 

 

 

 

 

 

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2 Replies
AminT_Intel
Employee
151 Views

Hello,

 

I apologize for the late response. They can be connected to any differential I/O. The selection criteria is based on whether the clock is going to capture the data directly or going to drive the PLL. You can also use dedicated pins to drive the global network if they are high speed and big fanout. I hope this answer helps and again I apologize for the late response. 

 

Thank you. 

AminT_Intel
Employee
127 Views

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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