ALTLVDS_RX inclok pin. Dedicated clock port?

[de10]

I'm designing an FPGA, using Enclustra Mercury PE1 and SA2. The FPGA is Cyclone V ST D6.
I'm trying to assign the data entry and clock pins. Someone knows if it is possible to connect the inclock input to any differential I/O. Or do I have to use dedicated clock pins (clk[0..7])?

Attach the image marking the pins dedicated to clk:

[AminT_Intel]

Hello,

I apologize for the late response. They can be connected to any differential I/O. The selection criteria is based on whether the clock is going to capture the data directly or going to drive the PLL. You can also use dedicated pins to drive the global network if they are high speed and big fanout. I hope this answer helps and again I apologize for the late response. 

Thank you. 

[AminT_Intel]

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