AN810 saws that the ADC and FPGA clocks need to be run off of the same source, different clocks. Why is this (clock drift, synchronization)? What clock source you used to drive the FPGA clock and the ADC Sample clock?

[IDeyn]

Hi TKunk1!

AN810 describes the case that's JESD204B standard requirement. Both the ADC and the FPGA must share the same clock. That's JESD204B standart requirement. Refer to"4.4. Clocking Scheme" of JESD204B User Guide for more information (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf)

I also want to mention that usually there are different ADC dev. boards which have own internal clock source which distribute clocks to both ADC and FPGA, and it that case you don't need an external clock source.  

In case of AN810 you should use external clock source for both devices. It could be same source or several sources with phase synchronisation.

Best regards,

Ivan

[TKunk1]

Thanks for the reply Ivan.

I looked at the link that you sent and It makes sense that the clock for the ADC and the FPGA need to be on the same frequency reference.

What I am still a little confused about is that the document that you sent says that the SYSREF and the ADC sampling clock need to have matched traces. However in AN810 (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an810.pdf), it shows that the FPGA is providing the SYSREF signal to the ADC board. I assume that the FPGA is providing a signal that is phase matched with the device clock which is synchronized with the ADC sample clock, but in the JESD204B users guide, it shows that the you need to match the traces between the ADC sample clock and the SYSREF clock to prevent phase offset. By using the FPGA to generate the SYSREF and then sending it to the ADC on another SMA cable it seems that you would be introducing more phase delay, which they are trying to prevent. Will this cause any problems or is the ADC not that sensitive to phase offset?

Thanks,

Tom

[IDeyn]

Hi Tom!

"It is not mandatory for the same SYSREF signal to be generated to all devices in the system. However, it is required that SYSREF signals be generated to all devices in a manner that ensures a deterministic relationship between when SYSREF is sampled active by all devices in the system." from JEDEC Standard No. 204B, Page 31.

Trace matching is a way to get correct timing relationships between SYSREF and ADC clock.

Required setup/hold time for ADC's SYSREF PORT you can see on page 10 ad9208 datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/ad9208.pdf).

Your system should meet these requirements to avoid problems with correct data transferring from ADC to FPGA.

Design, as you can see in AN810, should be constrained with set_output_delay timing constraints of SYSREF_IO to provide correct setup/hold timing for ADC's ports.

Best regards,

Ivan

[TKunk1]

Ok.  That makes sense.  Thanks for your help Ivan.