I would like to know more detail about RMII interface timing.
I wrote 2 quiestions below.
(I send 50MHz CLK to HPS EMAC as a REF_CLK from phy chip.)
1)Do you have any reguration for R_CLK?
For example frequency,duty ,rise time ,falltime.
If you have,please show me reguration with voltage level.
I could confirm on datasheet only TX_CLK reguration but couldnt find about RX_CLK.
2)Which edge the HPS EMAC ratched RX_D/RX_CTL signals.
I added figure to support my poor English.
If I am not wrong the above diagram is from from the below user guide and the pins used in transceiver.
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