Please provide us with the SI Analysis reports of ARRIA 10. I find that missing in the folder.
Like the SI Analysis report for the Cyclone V SOC Kit has been of extreme help when the board
design was done. The same way we will be very thankful If we can get the SI analysis reports
for various critical interfaces of ARRIA 10 SOC Kit - DDR4 (FPGA, HPS), SFP+, etc. etc....
Can some one also please provide us with the PCB layout files (CAD / GERBER) for the HiLO
Memory Cards. It will be really very helpful for the board design.
We thank the community for your support.
Thank you for using Intel Community.
May I know which development kit that you used?
How do you find the SI Analysis is missing?
"Can some one also please provide us with the PCB layout files (CAD / GERBER) for the HiLO
Memory Cards. It will be really very helpful for the board design."
- Sorry, we are not able to provide the PCB layout for Hilo daughters card.
Thank you for your kind response.
We are using ARRIA 10 SOC Development Kit:-
When I checked the board files, we could not locate the SI Analysis reports, maybe I am missing something here. It was there in CYCLONE V SOC KIT :-
Can you please provide us ARRIA 10 Reference boards where DDR3/4 on FPGA/HPS side is there, if possible as components on board rather than Daughter Cards? Will be really thankful. Will do a detailed SI Analysis on the KIT and Our Board before finalizing our boards as it will be having a good production value later on and we do not want versions of any kind.
The report might not be available for Arria 10 devkit.
Usually I don't see the report in the board package file for Arria 10 device.
I will try to check with the engineering if the report is available for the Arria 10 device,
Also, usually the user will do their own board simulation to get the accurate parameter setting.
The external memory interface can only be connected through the Hilo port on the board.
The medium between the memory and Hilo is the daughter card.
You can still refer to the board schematic and also pin connection guideline in the link below.
You can use the Board Skew Parameter Tool to identify the board skew.
Could you check with your team on the report? A gentle reminder to pass on the same to us.
All the possible and important steps highlighted by you are being followed but still a solid reference from THE INTEL helps us so that we do not select wrong IBIS Models during simulations or at least compare the same with a reference. Besides DDR4 still remain very important for us so that we are not making mistakes in the Layout.
Helps generate more confidence as huge amount of money is on stake while these 10 systems are getting developed.
Thanks AdzimZM once again for your prompt replies and please excuse me for my delayed response here.