ARRIA10 GX-DDR4

[vivekt]

I am designing a board with Arria10GX with DDR4 module. 

The input DDR4 Ref clock for the FPGA is LVDS  (133.33MHZ) and is generated by a clock generator  .

However the pinout provided by the RTL team maps the pin to a 1.2V Bank.(SSTL/POD) . Will the bank support a LVDS clock input

I have also checked the Arria 10 FPGA Development Kit schematics. Even there LVDS Clock is connected to Bank 2k (1.2V) .   

Is it ok to connect LVDS clock to 1.2V Bank. Kindly clarify

[Ash_R_Intel]

Hi,

In the Arria 10 GX FPGA development kit, the memory related connection are made to a connector. It can be connected to different types of memories like DDR3, DDR4, RLD3 etc. The reference design top is also not assigned with any IO standard in the qsf file. 

Please refer 

https://www.intel.com/content/www/us/en/programmable/documentation/sam1403483633377.html#sam1403481946777, Table 33 for the required voltages for different I/O standards.

As per the table, you can interface with a LVDS input signal only if VCCPT of the bank = 1.8V.

Regards

[vivekt]

My query is regarding the input DDR Clock to the FPGA  present in Bank 2K and not the connector side.  

As per the schematic the Voltage connected to Bank2k is A10_VCCIO_MEM -(supporting voltages 1.2V/1.25V,1.35V,1.5V )

In the design nets CLK_EMI_P/CLK_EMI_N are used to generate LVDS clock of 133.33MHz for DDR Bank2K .

Attached image from reference design(Arria 10 GX FPGA Development Kit)

[Ash_R_Intel]

VCCPT is connected to 1.8V in the schematic. So, as per the link that I shared earlier, LVDS signal can be connected to it.

Regards

[vivekt]

One more query regarding the Clock . If we look at the reference design for Bank 2I they have mentioned use OCT(an remove the 100R termination) , while for the bank 2K (DDR Bank) they do not want to use OCT. Is there any specific reason why we should not use OCT for DDR Bank

[Ash_R_Intel]

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