FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5925 Discussions

ASI OpenCore IP Compilation Error

Altera_Forum
Honored Contributor II
1,219 Views

Hi, 

I try to compile the cvdb_demo.qpf QuartusII project with the ASI OpenCore IP. I got the following error messages: 

 

Error: Node instance "asi_megacore_top_inst" instantiates undefined entity "asi_megacore_top" File: ../asi/source/mc_build/asi_rx.v Line: 65 

 

It seems to me that the asi_megacore_top is not defined in any .v file.  

Also this project is for QFP device. Can it be compiled for CycloneIII device? 

 

Please help. 

David
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
461 Views

i'm not familiar with this design, is there an SOPC Builder system you can regenerate before you compile?

0 Kudos
Altera_Forum
Honored Contributor II
461 Views

According to the user guide, http://www.altera.com/literature/ug/ug_asi.pdf, Cyclone III should be supported.

0 Kudos
Altera_Forum
Honored Contributor II
461 Views

Hi, 

 

Thank you for your reply. But I need a working example for a jump start. The example code comes with the installed IP seems not working.  

 

Thanks, 

David
0 Kudos
Reply