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4960 Discussions

AVGT development board PCIe and SFP pin assignment

Honored Contributor I

can i use pcie and sfp on the AVGT development board's FPGA1 at the same time?

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4 Replies
Honored Contributor I

Let me see ... The Arria V GT kit ... 




Yeah, sure, I don't see why not. 


Please download the installation for the kit and compile some of their example designs, I'm pretty sure you'll see that they have different top-level pin assignments, and connect to different transceiver banks on the FPGA. In fact, that information is probably in the reference guide for the kit too. 


Take a more detailed look at the kit documentation, and if there is a specific question not answered in the documentation, people on this list will be able to answer your question. 


If you already have this kit, then notice that they only have design files for Quartus 12.1. My experience with Altera kits in-general is that its a good idea to have exactly that version of Quartus installed when you first use the kit, since the board-test-system (BTS) that usually ships with the kits does not always work with newer versions of Quartus. Once you've got a working design, you don't need the BTS GUI, but its a good way to check that your hardware works. 



Honored Contributor I

when i fit the project(only include pcie ),it can success. 

when i fit the project(pcie and sfp),when fitting,show below. 




Error (12857): HIP reset pin "perstn" is locked to "PIN_N9", which is not legal. 

Error (11688): hip_serial_tx_out3(n) is assigned to PIN_AL36, sfp_tx_p_2 is assigned to PIN_J37, channels cannot be placed in the same quadrant. 

Error (11688): hip_serial_tx_out3(n) is assigned to PIN_AL36, sfp_tx_p_1 is assigned to PIN_W37, channels cannot be placed in the same quadrant. 




Honored Contributor I

I'm not sure. I'd recommend filing a Service Request with Altera directly and asking them to clarify. 


The error message indicates that the SFP transceiver is in conflict with the PCIe ... but that would be a pretty annoying design error, so hopefully its just an incorrect tool setting. 


What you could do is try to create a PCIe design with a x1 lane instead of the x4 or x8 lanes that their example design uses and see if the error is resolved. Hopefully the SFP channel is in the bank with the MSBs of the PCIe and this work-around will work; actually, the error message indicates that the conflict is with HIP bit 3, so a x1 design might still be in conflict ... You'll just have to try it and see. If this works, you will reduce your PCIe bandwidth, but hopefully that is ok (its better than no PCIe at all!). 



Honored Contributor I

To lihaiquan, 


I'l having a similar problem: after assigning some output pins I get the error: 

Error (12857): HIP reset pin "i_pcie_perst" is locked to "PIN_BD35", which is not legal. 


The pins that I assigned are output signals which goes to the transceiver, and are placed in: 

set_location_assignment PIN_W41 -to o_serial_data_GBT[0] 

set_location_assignment PIN_U41 -to o_serial_data_GBT[1] 

set_location_assignment PIN_R41 -to o_serial_data_GBT[2] 

set_location_assignment PIN_L41 -to o_serial_data_GBT[3] 

set_location_assignment PIN_N41 -to o_serial_data_GBT[4] 

set_location_assignment PIN_J41 -to o_serial_data_GBT[5] 



As you can see they are quite far from PIN_DB35, which is the one giving problems. The funny thing is that if I don't assign any pin to o_serial_data_GBT then the error goes away. 


Did you still remember what you had to do to solve the problem? 


Thanks in advance. 


PD: somehow related to this: http://xkcd.com/979/