AXI Bridge test in Stratix-10 EVM

[Tirupataiah]

Hi,

I am unable to test the HPS->FPGA AXI bridge in Stratix-10 H-Tile Dev Kit. Please provide the reference example or document to test the HPS->FPGA AXI bridge in the Stratix-10 Dev Kit.

Thank you.

[JingyangTeh]

Hi Tirupataiah

Could you please share what kind of test you are looking for?

Are you looking at some stress test for the axi bridge?

Regards

Jingyang, Teh

[Tirupataiah]

Hi JingyangTeh,

I am trying to write from HPS and read from FPGA using this AXI bridge. How i can proceed with the basic design from FPGA and HPS side. Basic write and read operations only i want to try. 

Please help me regarding this in Stratix-10 Dev Kit.

[JingyangTeh]

Hi Tirupataiah

Once booted into linux, you could read or write to the memory location with the md command.

You could refer to the link below for the register map.

https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html

To communicate through the HPS-to-FPGA bridge.

You can start write/read from the base address of 0xC0000000.

For the device that is connected to the bridge that you would like to interact with you could find the offset from the platform designer.

You could refer to the base column.

Please ignore the other IPs, the photo below serves the purpose of showing where the base address is.

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Any update on this case?

Regards

Jingyang, Teh

[JingyangTeh]

Hi

Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh