Hi everyone
About FPGA:
Does Cyclone V (5CEA7 F896) support DDR3? If you support it, can you help provide the next user guide? It has a dedicated pin for DQS and ADDRESS. Can you help provide guidance manuals in this regard?
Another question, could you please help to provide the design reference of USB3.0。
Link Copied
You can use the EMIF spec estimator to see what's supported:
All EMIF IP documentation for older devices like CV can be found here:
Cyclone V device overview document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdf
Cyclone V Device handbook , chapter 6 explains guidelines of using DQ/DQS pins : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
For more complete information about compiler optimizations, see our Optimization Notice.