About fpll recalibration failure problem of transceiver (simplex tx) under cyclone 10

[lambert_yu]

Hi,

   I am facing one problem, which is about fpll recalibration failure on cyclone 10 board. Just for same .pof file, no timing violation and different cyclone 10 boards, after POR, the transceiver can ru n normally for two boards; When switch to another refclk of fpll which is used for simple tx transceiver, one board can recalibration normally, the other is usually failure, I found that the cal_busy of fpll is high and not change to low, that means fpll failed when recalibration, I have no idea about this, could someone help me?

Brs,

Lambert

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquiries related to the fPLL recaliration after perform a refclk switching to the fPLL. It seems like the fPLL cal_busy remains high. Just would like to check with you on the following:

1. Just wonder if you have had a chance to try running Modelsim simulation with your design before to isolate any potential functional issue prior to hardware testing?

2. Would you mind to share the detailed steps that you are using to perform the fPLL recalibration? You may cross checked with the section "Fractional PLL Recalibration" in the C10GX XCVR PHY user guide on the steps.

3. Just to check with you if the CLKUSR and fPLL refclk are directly sourced from free-running and stable on-board oscillators?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[CheePin_C_Intel]

Hi,

Please help to check if the RREF pins of your device are connected individually to 2k Ohm resistor to GND.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[lambert_yu]

Hi CheePin,

    Just for your question, I make sure that 1,3,4 all are satisfy and for 2, step 1: get bus access; step 2: switch one reference clock to another reference clock; step 3: send recalibration command; step 4: release bus access; step 5: wait for the completion of recalibration.

    For another thing, I try 3 boards(all same, except fpga chip), 2 boards work normally, and another usually has this problem.

Brs,

Lambert

[lambert_yu]

+fpga chip : 10cx150yu484e6g

  software : quartus 17.1

[CheePin_C_Intel]

Hi Lambert,

Thanks for your clarification. Based on your responses, there seems to be no issue with the clocks and your recalibration steps. Also, it seems like 2 boards are working but 1 is not. This seems to be something specific to the failing board. Just wonder if you have had a chance to check the following:

1. XCVR related power supplies to see if there is any anomaly with the failing board?

2. Have you got a chance to try with different fPLL to see if similar issue persists? Just to narrow down to specific fPLL only or all fPLLs are showing similar symptom in the failing board.

3. You might also want to use oscilloscope to check on the refclk eye diagram to see if there is any anomaly vs datasheet specs?

4. Just to check after refclk switching, if there is any other fPLL configuration that you are dynamically reconfiguring?

Please let me know if there is any concern. Thank you.

[lambert_yu]

Hi CheePin,

    Thanks for your suggetion, now I have found the root cause which is about the cal_busy signal, it's one async signal, the method I use this signal has problem.

Brs,

Lambert

[CheePin_C_Intel]

Hi,

Thanks for your update. Glad to hear that you have managed to root cause and resolve the problem. Thank you.