According to the Intel MAX 10 Clocking and PLL User Guide, there is an option to turn off the internal oscillators, in this case what are the phase noise requirements when using an external oscillator?

[JonWay_C_Intel]

Hi @ABars4​ 

I do not understand what is the correlation of turning off the internal osc with your question on phase noise requirement with ext osc?

Could you elaborate what is your intention and end goal?

[ABars4]

Sorry I didn't phrase my question correctly, I am referring to the internal oscillators. What I am trying to find out is the phase noise requirements for the PLLs from the reference clock. I am trying to understand what specifications an oscillator will need to meet to drive the reference clock. Phase noise masks are available for other Intel FPGA boards under PLL and Transceiver specifications but I wasn't able to find it for the MAX 10.

[JonWay_C_Intel]

For MAX 10 PLL, you will need to meet the Input clock cycle-to-cycle jitter. See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf (Table 27)

[JonWay_C_Intel]

Btw, you cannot drive the PLLs with internal oscillator.

See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf (Section 3.2.1)