Agilex 7 HPS SPI register

[Kiebach]

Hello,

This site shows the memory map of the Agilex 7 HPS:

Intel Agilex® 7 Hard Processor System Address Map and Register Definitions - Hard Processor System (HPS) Address Map for the Intel Agilex 7 SoC

When I read the SPI Master registers, I get only ZEROs?!?  What is amiss?!?

CTRLR0...........00000000
CTRLR1...........00000000
SSIENR...........00000000
MWCR.............00000000
SER..............00000000
BAUDR ...........00000000
TXFTLR...........00000000
RXFTLR...........00000000
TXFLR............00000000
RXFLR............00000000
SR...............00000000
IMR..............00000000
ISR..............00000000
RISR.............00000000
TXOICR...........00000000
RXOICR...........00000000
RXUICR...........00000000
MSTICR...........00000000
ICR..............00000000
DMACR............00000000
DMATDLR..........00000000
DMARDLR..........00000000
IDR..............00000000
SSI_VERSION_ID...00000000
DR0..............00000000
DR1..............00000000
DR2..............00000000
DR3..............00000000
DR4..............00000000
DR5..............00000000
DR6..............00000000
DR7..............00000000
DR8..............00000000
DR9..............00000000
DR10.............00000000
DR11.............00000000
DR12.............00000000
DR13.............00000000
DR14.............00000000
DR15.............00000000
DR16.............00000000
DR17.............00000000
DR18.............00000000
DR19.............00000000
DR20.............00000000
DR21.............00000000
DR22.............00000000
DR23.............00000000
DR24.............00000000
DR25.............00000000
DR26.............00000000
DR27.............00000000
DR28.............00000000
DR29.............00000000
DR30.............00000000
DR31.............00000000
DR32.............00000000
DR33.............00000000
DR34.............00000000
DR35.............00000000
RX_SAMPLE_DLY....00000000
RSVD_1...........00000000
RSVD_2...........00000000

Note that I am using a Agilex™ 7 FPGA I-Series Development Kit (ES1 2x R-Tile & 1x F-Tile) DK-DEV-AGI027R1BES (Power Solution 1) AGIB027R29A1E2VR3.

Thanks.

[Kiebach]

The HPS TRM has a section "B.2. Taking Ownership of Quad SPI Controller" where it says that the bootloader takes control of the SPI Controller from the SDM.  This section is vague and does not supply any specific details as to how this is done.  My next step will be to study u-boot to see how this is accomplished.  If anyone at INTEL can provide assistance it would be appreciated...

[Kiebach]

Hello,

The mbox_qspi_open() function calls mbox_send_cmd() function as shown below.  The error message is:

/* Invalid license for IID registration */
MBOX_RESP_PUF_ACCCES_FAILED = 0x80,

I do not know what this error message indicates.

Can anyone help?

int mbox_qspi_open(void)

{

int ret;

u32 resp_buf[1];

u32 resp_buf_len;

ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,

    0, NULL, 0, 0, NULL);

if (ret) {

/* retry again by closing and reopen the QSPI again */

ret = mbox_qspi_close();

if (ret)

return ret;

ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,

    MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);

if (ret)

return ret;

}

/* HPS will directly control the QSPI controller, no longer mailbox */

resp_buf_len = 1;

ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,

    0, NULL, 0, (u32 *)&resp_buf_len,

    (u32 *)&resp_buf);

    printf("PRK ret = %X\n", ret);

if (ret)

goto error;