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IDeGu
Beginner
213 Views

Altera DE-10-Nano UART Rx and Tx in Pin Planner

Hi there,

 

I'm doing a NIOSII tutorial but I got stuck to the UART pins assignment in the Quartus Pin Planner. Specifically I have to connect the Rx and Tx to their respective pins.

 

Capture.PNG

 

 

Since I have a DE10-Nano version C, I had a look on the various documents and it appears that the connection must be done with the pins A22 and B21.

Capture.PNG

 

But when I try to assign the pins the below happens:Capture.PNG

Pins rx and tx are the external_connection of the UART (RS-232 Serial Port) Intel FPGA IP.

 

Any suggestion on what I 'm doing wrong, please?

 

Thanks, any help appreciated!!

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8 Replies
Deshi_Intel
Moderator
164 Views

HI,

 

Looking at your Table 3-17 screen shot, UART pins should be assigned to 3.3V IO standard but your pin planner UART pins are still configured to 2.5V IO standard

 

Try to correct the IO standard setting in pin planner.

 

Another thing to take note is one FPGA IO Bank can only accept one type of IO standard.

  • For instance, you can't have one IO bank that has some pins assigned to 2.5V IO standard and some pins assigned to 3.3V IO standard.

 

Thanks.

 

Regards,

dlim

IDeGu
Beginner
164 Views

Hi dlim,

 

thank you for your answer. You have a good point, as I missed the I/O Standard Voltage column: well spotted.

Unfortunately the result does not change and still I have the error message "Editing location assignment is not successful. Not assignable" . At this point I am wondering if I am supposed to assign the UART pins or if it is done automatically.

 

I would appreciate more inputs if you spot something else, please :)

Thank you again,

Iggy

 

Deshi_Intel
Moderator
164 Views

Hi,

 

I checked the schematic. Pin A22 and pin B21 are dedicated FPGA HPS pin with multiple function supported.

 

I know for sure you need to configure HPS IP to set the pin_mux to switch the pin function to function as UART pins but I am not sure whether do you still need to set the pin setting in Quartus Pin Planner or not.

 

I suggest you open any example design from DE-10 NANO board to learn how they set the pin setting accordingly.

 

Thanks.

 

Regards,

dlim

IDeGu
Beginner
164 Views

Good point dlim!

 

I have discovered a program utility called System Builder that was shipped with the unit. Basically it generates a Quartus project with the pin declarations that you need and bypass the troubles I had with Pin Planner.

Capture.PNG

 

It ended up working correctly and I took some time looking into the generated files.

The below is part of the Verilog file which is generated by the System Builder:you can see the HPS pins being assigned in what is intended to be the top file.

//======================================================= // This code is generated by Terasic System Builder //=======================================================   module DE10_NANO(   //////////// CLOCK ////////// input FPGA_CLK1_50, input FPGA_CLK2_50, input FPGA_CLK3_50,   //////////// HPS ////////// inout HPS_CONV_USB_N, [...] input HPS_UART_RX, output HPS_UART_TX, [...]   //////////// KEY ////////// input [1:0] KEY,   //////////// LED ////////// output [7:0] LED,   //////////// SW ////////// input [3:0] SW,   //////////// GPIO_1, GPIO connect to GPIO Default ////////// inout [35:0] GPIO );   endmodule  

While in the QSF file you can see the pins being assigned.

#============================================================ # Build by Terasic System Builder #============================================================ [...]   #============================================================ # CLOCK #============================================================ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 set_location_assignment PIN_V11 -to FPGA_CLK1_50 set_location_assignment PIN_Y13 -to FPGA_CLK2_50 set_location_assignment PIN_E11 -to FPGA_CLK3_50   #============================================================ # HPS #============================================================ [...] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX [...]   #============================================================ # End of pin assignments by Terasic System Builder #============================================================

Still I'm unsure how I was supposed to know that, but maybe I missed it somewhere in the number of tutorial I checked on the topic.

 

Thank you again dlim, I appreciated a lot your input!

Iggy

Deshi_Intel
Moderator
164 Views

Hi Iggy,

 

Looks like you found some special software tool developed by Terasic to deal with pin assignment issue.

  • FYI... this is Intel FPGA forum. Perhaps it's better if you check with Terasic directly since you are using their board and also their software tool
  • You can contact Terasic support via support@terasic.com

 

But even if I look at the terasic software screen shot, it only assign IO standard to UART pins but not the actual pin location itself. So, maybe you don't need to assign the pin location after all. You can check Quartus fitter report later to verify whether UART pins is auto assigned to correct pin location or not.

 

Also like I said, make sure you have configured the IO pin mux setting correctly in HPS IP as these are multiple function IO pins.

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
164 Views

Hi Iggy,

 

I have not hear back from you for sometime.

 

Hopefully you found my debug suggestion useful and also able to contact Terasic for further support.

 

For now, I am setting this case to closure.

 

Thanks.

 

Regards,

dlim

IDeGu
Beginner
164 Views

Hi dlim,

 

thank you for your reply. Yes, please close it, the issue with Pin Planner has been resolved using System Builder.

 

Cheers,

Iggy

Deshi_Intel
Moderator
164 Views

Alright, good to know !

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