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Valued Contributor III
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Altera DE2-115 compatibility with HSMC-ADC-BRIDGE

I've already got an Altera DE2-115 board and I'm planning to use it together with a high speed ADC EVM by Texas Instruments for a measurement application. 

I've found in the "All Daughter Cards" page on the Altera website the item "TI ADC to HSMC Adaptor" which would be very useful for my case. 

So my questions are: 

_Is the Altera DE2-115 board compatible with this adaptor?  

_Can I be sure of the DE2-115 board compatibility with all TI's ADC EVMs compatible with this adaptor? If not, which aspects should I be careful of to verify compatibility? 

 

Regards, 

Lorenzo
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Valued Contributor III
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--- Quote Start ---  

 

Is the Altera DE2-115 board compatible with this adaptor?  

 

--- Quote End ---  

Look on p15 of the DE-115 schematic. It shows the pins that are connected to the HSMC connector. Since the signals are named P/N its highly likely that these pins are connected to LVDS signals on the FPGA. If you look on p23, you will see that the signals are indeed connected to pins that can be configured as LVDS. The high-speed transceiver lanes on the HSMC are not connected. 

 

If the TI board uses the transceiver lanes, then this board would not be useful to you. 

 

 

--- Quote Start ---  

 

Can I be sure of the DE2-115 board compatibility with all TI's ADC EVMs compatible with this adaptor? If not, which aspects should I be careful of to verify compatibility? 

 

--- Quote End ---  

Compare the schematics of the TI EVMs to the HSMC specification and to the Altera board. 

 

The LVDS signals on the HSMC can be configured as LVDS or single-ended I/O. If you look on p27 of the schematic, you will see that VCCIO for the HSMC connector can be set using a jumper. If the TI EVM board HSMC connector uses the pins in the LVDS section of the connector, then you need to check whether the FPGA needs to interface using 2.5V LVDS or 1.5/1.8/2.5/3.3V LVCMOS. 

 

If the TI EVM uses the transceivers, then the DE-115 board will not work. If you do need to use a board with transceivers, the DE4 board would probably work for you. Any required AC coupling due to common-mode incompatibilities should be on the EVM. However, you would need to check. 

 

Cheers, 

Dave
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Valued Contributor III
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First of all, thank you for replying: as you can see I really need help =) 

 

I can compare pins of HSMC connector on p13 of DE2-115 schematics (am I on the wrong page?) with the ones of the male HSMC connector provided by the TI adapter: every pin on the TI board is also on the female HSMC on the DE2-115. Now, if I got what you said I have to verify if all of these pins come to the FPGA: the only ones I can't find on p25 are HSMC_SDA and HSMC_SCL. Are they the high-speed "trainscever lanes" you were referring to? (sorry, I'm a complete beginner with this kind of problems) 

Anyway, if they are I can read on DE2-115 User Manual that "Signals HSMC_SDA and HSMC_SCLK share the same bus with the respected signals I2C_SDA and I2C_SCL of the WM8731 audio chip": I looked for them on DE2-115 schematics and they're found on the Bank 8. Am I missing something? 

 

About the second answer you gave, I need to think a bit longer about it before probably  

asking some more =) 

 

Regards, 

Lorenzo
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--- Quote Start ---  

 

I can compare pins of HSMC connector on p13 of DE2-115 schematics (am I on the wrong page?)  

 

--- Quote End ---  

Yes, I meant p13, sorry. 

 

I've attached the schematic from the DE2_115_v.1.0.5_SystemCD so you have the same version. 

 

 

--- Quote Start ---  

 

I can compare pins of HSMC connector on p13 of DE2-115 schematics (am I on the wrong page?) with the ones of the male HSMC connector provided by the TI adapter: every pin on the TI board is also on the female HSMC on the DE2-115. 

 

--- Quote End ---  

Ok thats a good start. Why don't you post the TI EVM schematic PDF, or post a link to the PDF on TI's web site. 

 

 

--- Quote Start ---  

 

Now, if I got what you said I have to verify if all of these pins come to the FPGA: the only ones I can't find on p25 are HSMC_SDA and HSMC_SCL. Are they the high-speed "trainscever lanes" you were referring to? (sorry, I'm a complete beginner with this kind of problems) 

 

--- Quote End ---  

No. These are I2C connections. If the TI kit does not use them, its no problem. 

 

 

--- Quote Start ---  

 

Anyway, if they are I can read on DE2-115 User Manual that "Signals HSMC_SDA and HSMC_SCLK share the same bus with the respected signals I2C_SDA and I2C_SCL of the WM8731 audio chip": I looked for them on DE2-115 schematics and they're found on the Bank 8. Am I missing something? 

 

--- Quote End ---  

So long as the TI kit does not short these pins to ground, the DE115 I2C bus will work fine. 

 

 

--- Quote Start ---  

 

About the second answer you gave, I need to think a bit longer about it before probably asking some more =) 

 

--- Quote End ---  

No problem. Ask questions when you are ready. 

 

Cheers, 

Dave
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Valued Contributor III
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--- Quote Start ---  

The high-speed transceiver lanes on the HSMC are not connected. 

If the TI board uses the transceiver lanes, then this board would not be useful to you. 

--- Quote End ---  

 

On the HSMC specifications I could find trainscever lanes and only now I'm sure my TI adapter board doesn't use them (I'm attaching the TI adapter and EVM schematics). 

 

 

--- Quote Start ---  

If you look on p27 of the schematic, you will see that VCCIO for the HSMC connector can be set using a jumper. If the TI EVM board HSMC connector uses the pins in the LVDS section of the connector, then you need to check whether the FPGA needs to interface using 2.5V LVDS or 1.5/1.8/2.5/3.3V LVCMOS. 

--- Quote End ---  

 

On DE2-115 schematic p27, I can see how HSMC_VCCIO is set: does this setting have influence on LVDS transmission or is it only for LVCMOS?  

 

I've got also another question: on the same page I can see a set of resistors between each pair of Rx lines, as they're needed for LVDS to work properly (they should be 100 ohm resistors, right?). What does DNI stand for? Is it for "Do Not Install"? Should I care about it? 

 

TI ADS58B19EVM board uses LVDS section pins as LVDS lines: if I got the problem, I should then verify common and differential mode signal on these lines. The ADC LVDS output lines come directly on the connector of the EVM board, so if I don't go wrong I have to look at the ADC datasheet. 

I can find there a LVDS output of +/- 350 mV with a common mode 0.85 V < VCM < 1.25 V. On the Cyclone IV datasheet (p14) I can find LVDS input requirements of minimum 100 mV differential and an overall common mode range of 0.05 V - 1.55 V (actually it changes with operating speed, but I think the slowest speed of 500 Mbps should be already sufficient for me), so it should be okay. Does it make sense or I'm missing something? 

 

Regards, 

Lorenzo
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--- Quote Start ---  

 

I'm attaching the TI adapter and EVM schematics 

 

--- Quote End ---  

Ok, thanks. 

 

So from their adapter board schematic, you can see that the connections to the HSMC;  

 

* 16-bit LVDS data and two LVDS clocks. 

* some single-ended signals to HSMC_D0, 1, and D2 on the DE115 HSMC connector. You'll need to check those logic levels, and their direction. 

* some single-ended signals to HSMC_SCL,SDA - you'll also need to check those logic levels, and their direction. The DE115 board uses these signals for I2C, whereas from the TI names I suspect SPI. You need to be careful that the TI board is not expecting to drive these signals, since the DE115 device will too. If both devices were I2C, this would be ok, since I2C is open-drain. However, if the TI device is thinking an SPI slave is on those wires, then it can drive active high, and if the FPGA or an I2C device on the DE115 drives active low, you might damage the device. 

 

 

--- Quote Start ---  

 

On DE2-115 schematic p27, I can see how HSMC_VCCIO is set: does this setting have influence on LVDS transmission or is it only for LVCMOS?  

 

--- Quote End ---  

It must be 2.5V for LVDS. 

 

 

--- Quote Start ---  

 

I've got also another question: on the same page I can see a set of resistors between each pair of Rx lines, as they're needed for LVDS to work properly (they should be 100 ohm resistors, right?). What does DNI stand for? Is it for "Do Not Install"? Should I care about it? 

 

--- Quote End ---  

p23 you mean? 

 

You would need to check whether the Cyclone device support on-chip 100-Ohm termination. If it did, then I would not expect to see these external resistors ... so there is a good chance you need these resistors for LVDS operation. DNI does mean 'do not install', so you will need to install the resistors. 

 

 

--- Quote Start ---  

 

TI ADS58B19EVM board uses LVDS section pins as LVDS lines: if I got the problem, I should then verify common and differential mode signal on these lines. The ADC LVDS output lines come directly on the connector of the EVM board, so if I don't go wrong I have to look at the ADC datasheet. 

I can find there a LVDS output of +/- 350 mV with a common mode 0.85 V < VCM < 1.25 V. On the Cyclone IV datasheet (p14) I can find LVDS input requirements of minimum 100 mV differential and an overall common mode range of 0.05 V - 1.55 V (actually it changes with operating speed, but I think the slowest speed of 500 Mbps should be already sufficient for me), so it should be okay. Does it make sense or I'm missing something? 

 

--- Quote End ---  

No, you did not miss anything, you've done that analysis nicely. The ADC and FPGA are defining their interface as 'LVDS' which means they are both adhering to the LVDS logic standard, so you can DC couple them without issues. The potential issue you could face would be that if your ADC LVDS goes above 800Mbps, the Cyclone might not be able to work, but for 500Mbps, you should be ok.  

 

Even though the LVDS connections are logically compatible, you will still need to check the single-ended signals. Go back to the DE115 schematic, and find out the VCCIO of the HSMC single-ended signals. Then check there will be no driver conflicts with the SPI/I2C signals. 

 

Cheers, 

Dave
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Valued Contributor III
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--- Quote Start ---  

Even though the LVDS connections are logically compatible, you will still need to check the single-ended signals. Go back to the DE115 schematic, and find out the VCCIO of the HSMC single-ended signals. Then check there will be no driver conflicts with the SPI/I2C signals. 

 

--- Quote End ---  

 

 

 

As I can see from ADC EVM schematic, SPI lines on the output connector (SEN, SDATA, SCLK) are normally left floating on the board and one can choose to use them installing some resistors. So I should have no problem there since I can still communicate with SPI via USB connection, as the board permits to do. 

 

There are HSMC_D1 and HSMC_D2 left. HSMC_D1 is another SPI bus signal, used by a component on the TI board which I don't need to use (it can be isolated from the power supply by removing a jumper), so it shouldn't be a problem either. The only signal I need to use is on HSMC_D2, which is still connected to FPGA BANK 5 and carries an over-range output bit coming directly from ADC. Voltage levels for this ADC logic output are: VOH = 1.7 V and VOL = 0.1 V. 

 

So here's my first question: I've already set HSMC_VCCIO = 2.5 V for using LVDS. This setting has effect for all BANK 5 and BANK 6 pins, right? So for HSMC LVCMOS lines (from Cyclone IV datasheet p.12) it has to be: VIL = 0.7 V, VIH = 1.7 V. So I'm exactly on the threshold for the high logic state: is it going to be a problem without any solution? 

 

Actually, the same OVR signal from EVM board is repeated (can't understand why, maybe I'll ask to TI forum) on another output connector pin, which becomes INPUT3_M signal on HSMC connector: it is still the same 1.8 LVCMOS output, but it is carried on a single LVDS line. I think I won't need it, since I would have here the same situation I had on HSMC_D2, but is it going to be a problem having this undesired signal on INPUT3_M? 

 

Lastly, a curiosity: if I needed to use the LVCMOS signal on INPUT_3M line, would I be able to do it? Or else, can I independently program each pin of my Cyclone IV linked to HSMC connector to be LVDS or LVCMOS? 

 

Regards, 

Lorenzo
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--- Quote Start ---  

As I can see from ADC EVM schematic, SPI lines on the output connector (SEN, SDATA, SCLK) are normally left floating on the board and one can choose to use them installing some resistors. So I should have no problem there since I can still communicate with SPI via USB connection, as the board permits to do. 

 

There are HSMC_D1 and HSMC_D2 left. HSMC_D1 is another SPI bus signal, used by a component on the TI board which I don't need to use (it can be isolated from the power supply by removing a jumper), so it shouldn't be a problem either. The only signal I need to use is on HSMC_D2, which is still connected to FPGA BANK 5 and carries an over-range output bit coming directly from ADC. Voltage levels for this ADC logic output are: VOH = 1.7 V and VOL = 0.1 V. 

 

--- Quote End ---  

This all sounds good. You should have no trouble connecting the two boards. 

 

 

--- Quote Start ---  

 

So here's my first question: I've already set HSMC_VCCIO = 2.5 V for using LVDS. This setting has effect for all BANK 5 and BANK 6 pins, right? 

 

--- Quote End ---  

Yes; look at p25 of the DE115 schematic HSMC_VCCIO powers bank 5 and 6. 

 

 

--- Quote Start ---  

 

So for HSMC LVCMOS lines (from Cyclone IV datasheet p.12) it has to be: VIL = 0.7 V, VIH = 1.7 V. So I'm exactly on the threshold for the high logic state: is it going to be a problem without any solution? 

 

Actually, the same OVR signal from EVM board is repeated (can't understand why, maybe I'll ask to TI forum) on another output connector pin, which becomes INPUT3_M signal on HSMC connector: it is still the same 1.8 LVCMOS output, but it is carried on a single LVDS line. I think I won't need it, since I would have here the same situation I had on HSMC_D2, but is it going to be a problem having this undesired signal on INPUT3_M? 

 

--- Quote End ---  

DE115 schematic p23 shows that the single-ended signals come from bank 5, so they are 2.5V LVCMOS.  

 

From your comments, I assume the TI driver signals are 1.8V LVCMOS. 

 

Even though these two logic standards are not directly compatible, these voltages look compatible "enough". Plug the signals together and see if things work. If they don't, you know what the problem is, so you can then figure out a better solution. Since the TI device is driving to an FPGA input, you can't damage anything ... if it was the 2.5V driver driving a 1.8V receiver, then I would be a little more careful. 

 

 

--- Quote Start ---  

 

Lastly, a curiosity: if I needed to use the LVCMOS signal on INPUT_3M line, would I be able to do it? Or else, can I independently program each pin of my Cyclone IV linked to HSMC connector to be LVDS or LVCMOS? 

 

--- Quote End ---  

There's a couple of potential issues; 

 

1) Quartus might not let you. 

 

There are limitations as to what single-ended signals can be located next to LVDS signals. You'd have to try P&R to see if Quartus will let you. 

 

2) It depends if you have installed the LVDS terminations. 

 

INPUT_3M on the adapter board goes to an LVDS pin on the DE115. If you install the 100-ohm termination resistors on the DE115 board, then you essentially connect pairs of pins together as far as single-ended signals go. You could drive a single-ended signal on INPUT_3M, and tri-state INPUT_3P, but the signal driven on INPUT_3M would appear on INPUT_3P back at its source. If INPUT_3P is just dangling, and the signal on INPUT_3P was not too fast (since you would get coupling and reflections), then it might work ok. 

 

If you examine the schematics, and figure out that you are not going to short pins out, you can then just 'try it'. If your idea works, and its good enough to get your test completed, just go for it. Later when you design a system, you can take a little more care. Just keep in mind that prototyping is prototyping; you're allowed to violate the rules ... just so long as you are aware you are violating them. 

 

Cheers, 

Dave
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Clear and complete :)  

Thank you for your precious support, I've learned many useful things I could have hardly got without it.  

 

Regards, 

Lorenzo
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Hi Lorenzo, 

 

--- Quote Start ---  

Clear and complete :)  

Thank you for your precious support, I've learned many useful things I could have hardly got without it.  

 

--- Quote End ---  

You're welcome. 

 

Since you are testing ADCs, you might find these interesting reading: 

 

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf

 

Cheers, 

Dave
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