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Altera Development board+CFI FLash+and its Pins, can this be possible

Honored Contributor I

Dear Guys 


Thanks for all the help that you have provided. I am still currently trying to get the Flash working. I would like to know that Pins CE_N,WAIT,WP_N.CLK,RESET, ADV_N, should I be controlling these pin using my FPGA, as when I looked at the schematic of the development board from http://www.altera.com/literature/manual/cycloneiii_sb_3c25.pdf 


I had noticed that Pins CE,WAIT,WP,CLK,REST, are all connected to 2.v with a 5.1k resister and ADV is connected to ground with 5.1 k resister. This make the Flash asychronous and should I just worry about asserting the WE and OE pins. IF these pins are mean to be connected to 2.5V or Ground full time, and then my assigning these to pins on my FPGA, this will just cause some kind of problem? 


Thank You 



Yours Sincerely 


Dharmesh Joshi
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