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Altera\Intel Qsys DDR3 SDRAM Controller with UniPHY termination of RESET# pin

SDavi9
Beginner
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I am using the Altera Qsys DDR3 SDRAM Controller with UniPHY within a Cyclone V E device to interface to my DDR3 !

 

It states in the following DOC:-

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf

 

"... If your board is already using the SSTL-15 I/O standard, you do not terminate the RESET# signal to VTT."

 

However on the development board (DB5CGXC7) this resistor appears to be present in the schematic ?

 

Please could someone explain ?

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BoonT_Intel
Moderator
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Yes, it is not recommend to terminate the reset signal to any source include VTT

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd07212013_499.html

 

I am sorry to inform that the dev kit do not follow the recommendation. However, it is still functioning correctly. Please note that this is recommendation but not a hard rules.

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