I am using the Altera Qsys DDR3 SDRAM Controller with UniPHY within a Cyclone V E device to interface to my DDR3 !
It states in the following DOC:-
"... If your board is already using the SSTL-15 I/O standard, you do not terminate the RESET# signal to VTT."
However on the development board (DB5CGXC7) this resistor appears to be present in the schematic ?
Please could someone explain ?
Yes, it is not recommend to terminate the reset signal to any source include VTT
I am sorry to inform that the dev kit do not follow the recommendation. However, it is still functioning correctly. Please note that this is recommendation but not a hard rules.