Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Beginner
875 Views

Altera\Intel Qsys DDR3 SDRAM Controller with UniPHY termination of RESET# pin

I am using the Altera Qsys DDR3 SDRAM Controller with UniPHY within a Cyclone V E device to interface to my DDR3 !

 

It states in the following DOC:-

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf

 

"... If your board is already using the SSTL-15 I/O standard, you do not terminate the RESET# signal to VTT."

 

However on the development board (DB5CGXC7) this resistor appears to be present in the schematic ?

 

Please could someone explain ?

0 Kudos
1 Reply
Highlighted
Moderator
17 Views

Yes, it is not recommend to terminate the reset signal to any source include VTT

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

I am sorry to inform that the dev kit do not follow the recommendation. However, it is still functioning correctly. Please note that this is recommendation but not a hard rules.

0 Kudos