FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5283 Discussions

Altera\Intel Qsys DDR3 SDRAM Controller with UniPHY termination of RESET# pin

SDavi9
Beginner
1,041 Views

I am using the Altera Qsys DDR3 SDRAM Controller with UniPHY within a Cyclone V E device to interface to my DDR3 !

 

It states in the following DOC:-

 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi.pdf

 

"... If your board is already using the SSTL-15 I/O standard, you do not terminate the RESET# signal to VTT."

 

However on the development board (DB5CGXC7) this resistor appears to be present in the schematic ?

 

Please could someone explain ?

0 Kudos
1 Reply
BoonT_Intel
Moderator
183 Views

Yes, it is not recommend to terminate the reset signal to any source include VTT

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

I am sorry to inform that the dev kit do not follow the recommendation. However, it is still functioning correctly. Please note that this is recommendation but not a hard rules.

Reply