Altera Stratix IV GX FPGA fundamental communication DE4(EP4SGX230C2)

[Altera_Forum]

Hi everybody, 

  I am a newbie trying to figure out how to implement a fundamental communication between PC and the FPGA board using PCIe. Basically we have all the PHY data processing ready in the FPGA board, in the hope of withdrawing required data and configurations from the PCIe FIFO. What I need to do now is to transfer some required data configurations from PC to the FPGA board via PCIe for the use of PHY layer processing. https://www.alteraforum.com/forum/attachment.php?attachmentid=7325   There is this example in the DE4 user manual named "fundamental communication". The example has a user interface where I should be able to control the board's LED lights and buttons from PC and do basic data read/write. I am thinking maybe if I could get the example working and see how it actually functions, I could simply modify its source code of the PC interface according to ye needs and achieve the goal.   However according to the demonstration setup, at the 5th step I cant seem to find the target board “VID=1172, DID=E001” which stops me from going on. So first, could anyone spot the problem here?  Second, if anyone has done this, could I ask what the difference is between "Memory-Mapped Write and Read" and "FIFO Write and Read"? And which one should I use in my case? "A report dialog box will appear when the DMA/FIFO process is completed."--What has been transferred and where has it been stored?  Also, does my plan sound feasible to you great engineers? Or what would you do if you were me?   I am sorry I asked lots of silly questions here, but this is all so new to me. Any help would be appreciated. Thank you.    Jane

[Altera_Forum]

.............Anyone？:(