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Altera_UP_SD_Card_Avalon_interface on DE10-Nano: pin assignement problem

francesco_simonetti
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I am trying to use the SD card of the DE10-Nano board for writing data in real-time.

I am using the IP named Altera_UP_SD_Card_Avalon_interface.

The problem arises when I try to connect the 4 pins of the IP to the physical  Micro SD card socket.

I connect the four pins as written in the DE10-Nano user manual (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwjNkLv-zJr9AhUNtKQKHaP-C5wQFnoECA8QAQ&url=https%3A%2F%2Fwww.terasic.com.tw%2Fcgi-bin%2Fpage%2Farchive_download.pl%3FLanguage%3DTaiwan%26No%3D1046%26FID%3D1c19d1d50e0ee9b21678e881004f6d81&usg=AOvVaw3fNmUCTp2a8PGm2lFNG1Sl

sd_card_b_SD_cmd=>PIN_D14,

sd_card_b_SD_dat=>PIN_C13,

sd_card_b_SD_dat3=>PIN_B9,

sd_card_o_SD_clock=>PIN_B8

and I have the following error:

Error (14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing constraints (4 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

> Error (175020): The Fitter cannot place logic pin in region (55, 81) to (55, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.

> Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:

> Error (184016): There were not enough single-ended bidirectional pin locations available (1 location affected)

How can I solve this problem?

Thank you very much.

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RichardTanSY_Intel
769 Views

You may navigate to this page and find the corresponding error message on the root cause and proposed solution.

It may helps to debug what might goes wrong with your design.

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#quartus/gl_quartus_welcome.htm


Error ID (175020):

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/efpp_no_locations_in_region.htm

Error ID (184016):

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/ecio_io_none.htm


Best Regards,

Richard Tan


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RichardTanSY_Intel
736 Views

May I know does my latest reply helps?


Best Regards,

Richard Tan


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RichardTanSY_Intel
704 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. 


Best Regards,

Richard Tan


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