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Altera cyclone 5 SoC cache debug mode

Honored Contributor II

Hi everybody, 

I'm trying to debug memory caches on the Altera cyclone 5 board, in particular on Terasic de0-nano-SoC. I'm using ARM DS-5 Ultimate Edition and the linux kernel running on my board is Linux socfpga 3.13.0-00298-g3c7cbb9-dirty. The big issue is that I cannot see cache memories in the debugger! The Data cache view is empty and the cache list comand returns No cache awareness for core "Cortex A9_0". 


I'm fairly sure that the caches (L1 and L2) are provided by the hardware. 

How can I resolve this?? 




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