Now I am design my development kit , the FPGA I am using is Stratix 2'S device EP2S180F1020C5N , I will use DDR2 soDIMM on my development . So , according to the Handbook , I must use the SSTL-18 class1 or class 2 IO specification on the hardware design . What amazing me is that this specification is just single-end communication specification , that is to say , the signal can transmit from FPGA to DDR2 , if the DDR2 data want to transmit to FPGA , the resistor will not match and may produce a serious reflection . Anyone who knows how to solute this problems please help me , it will be very kind of you!
In case of SSTL class 2, you have basically a two-sided termination. Board layout considerations may not allow a FPGA-side termination anyway. If termination mismatch and reflections are acceptable or not is mainly a matter of trace lengths and intended memory speed. Consult respective Altera application notes, particularly AN408 for a detailed discussion of expectable signal quality with different termination schemes.