Thank you for contacting Intel Community. Please be noted that Intel FPGA requires details information for failure analysis request. Please help to answer questions below in order for us to better understand your position.
1. Please provide full device details.
1.1. Device name:
1.2. Full part number:
1.3. Date code:
1.4. Lot number:
1.5. Trace code:
1.6. Distributor name:
2. What is the failure rate? What is the failure rate vs. tested sample? Example: 2 out of 100 units.
3. What is the failure symptom? Please elaborate the failure symptom in detail.
4. When did the failure happen? How did you discover the failure?
5. How did you determine the failure? Please elaborate the procedures.
6. Does the failure unit ever working before failure?
7. Did they violate solder re-flow temperature profiles, moisture sensitivity? Please provide the re-flow temperature profiles.
8. Did you swap the failure device to a known good board? Is the failure following the device or board?
9. May I know if this request comes from your side or end customer side? If the request is from end customer, please provide the end customer name.
10. Is this a prototype build or volume/mass production?
11. Kindly provide quantitative investigation result that could proof the failure is Intel FPGA induced.
Thanks for your replies. However based on your description,“F2 test” failure is too general to let us understand the actual failure behavior at your site. Board get passed after replacing the FPGA doesn’t lead us to conclude that it is due to the FPGA failure, as this failure could be due to board design margin or external factors during part replacement. Therefore, we would need customer to verify the suspected failure device on known good board. We also like to know what kind of the failure symptom exists at your site.
- What kind of function can’t work normally?
- Did you encounter any open/short failure?
- Any abnormality on the power rail performance?
- Any suspected failure pins?
Flex is contract manufacturer, may I know who the end customer of this product line?
Since there are only two signals “HDRXD0_OHP_PGA, HDTXD0_OHP_PGA”,The FPGA pins “R5,AB4”, would you please identify which FPGA pin tied to these 2 signals?