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EHait
Novice
474 Views

Arria 10 FPGA Development Kit - FMC Connections/Signals

All i want is to connect several LVDS RX links, each consist of 1 Rx clock and 9 RX data lanes to maximum it rate of up to 1,600 b/sec for each lane in DDR mode.

All LVDS signals of each interface off course should to be mapped to same io bank to achieve best timing.

 

But when i look at Dev Kit schematic i see that some of the signals names on FMC are marked as RX (like the FMCA_LA_RX_P/N9) and some of them are TX (like FMCA_LA_TX_P/N10).

But in the pin list in excel in column named "Dedicated TX/RX Channel" i see no difference between them and looks like all of them can be used as LVDS RX channels/data lanes.

 

Is it true?

What is the reason for that TX and RX marks in the schematic which so confusing me?

 

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3 Replies
Rahul_S_Intel1
Employee
85 Views

Hi , The FMCA is nomenclature the pin connection to FMC ,the pin out feature will be the same as per the pin out details which is explained in the Pin connection guidelines and pin out file
EHait
Novice
85 Views

Hi,

Can you be more specific? Can i or can't i use all of them for LVDS RX channels to 1,600 Mb/Sec DDR?

Or at least can you point to the right pin connection guideline file which holds the relevant information? Because i didn't find any timing info related to FMCA_LA_TX_P/N in LVDS RX mode....

Rahul_S_Intel1
Employee
85 Views

Hi , The pin connection guidelines is given below link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-v/pcg-01013.pdf There is no timing information in the above . The below document provides more information on EMIF https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf
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