Re: Arria 10 GX Devkit Programming Issue

Altera_Forum · ‎06-02-2017

When a scan jtag chain is performed on the devkit (all dip switches on default) after an image other than the factory build is programmed to the A10, the configuration flash is no longer seen in the jtag chain. Errors are reported back through the programmer that the flash is not supported by quartus.

We only do not see this issue when the factory default is programmed (i.e. customer image, board test builds, and example designs all produce this error).

Is this a known issue? If not, is it something in the rtl of the factory image that the customer is not including in their design?

Thanks

Altera_Forum · ‎09-12-2017

Hi avivweinstein,

I have the same issue on the devkit.

Actually, it's working sometimes, but on some fitting, the JTAG chain is broken...

Did you find a solution?

Regards,

Lionel

Altera_Forum · ‎09-12-2017

Are you plugging into the on-board USB-Blaster, using a USB-Blaster plugged into the JTAG port, or something else? When I use the on-board USB-Blaster I don't have problems--other than my USB cable falls out some times.

Altera_Forum · ‎09-12-2017

I'm using the on-board USB-Blaster.

The problem seems to be related to the fitting, despite the JTAG is a dedicated hardware controller, using dedicated pins.

Some of my bitstreams are not working at all while the others work perfectly (with some minor changes, such as revision ID)...

I also tried to reduce the JTAG clock frequency with no luck..

Regards

Altera_Forum · ‎09-13-2017

Oh, I see what you mean. Usually (80% of the time?) I don't see the configuration flash when executing a JTAG scan--not sure why. Would it work to save the .cdf when you *can* see the config. flash and use that .cdf every time after that?

Altera_Forum · ‎09-13-2017

Do you have the Altera SFL (serial flash loader) megafunction instantiated in the device image? The flash devices are NOT directly accessible on JTAG and are attached to the FPGA via high speed serial links. There is logic within the FPGA (the SFL megafunction) that must be instantiated that makes the config flash device appear in the JTAG chain as a virtual JTAG device.

It may very well be some of the sample images don't have this module instantiated, so they don't support JTAG access to the config flash.

Refer to: https://www.altera.com/ja_jp/pdfs/literature/an/an370.pdf for into.

Altera_Forum · ‎01-18-2018

Hi ak6dn,

Sorry for the delay...

Yes, I use the SFL for in-field programmation.

But the problem for me is not only accessing the EPCQ, but simply accessing the JTAG Chain.

Now, I have a serious problem on the board : The EPCQ does not containt any valid image, so it does not boot, AND the JTAG Chain is broken... Even if I power down/up, reboot the PC, tried with three different Altera Programmers....

Regards,

Lionel