Arria 10 GX FPGA Development Kit: DDR4 Example Design Fails Traffic Generator

[lcoon1981]

Hi,

I am using the Arria 10 GX Development Kit, Quartus Prime 22.1std2 Build 922 Standard Edition. Why the DDR4 example design is failing the traffic generator? Please tell me what I need to change in the IP so that it can pass?

I was following the Arria 10 FPGA IP Design Example User Guide to generate the example design.

The preset selected in the IP GUI is Arria 10 GX FPGA Development Kit with DDR4 HiLo. 

Looking forward to your response.

Thanks!

[AdzimZM_Intel]

Hi,

Thank you for submitting your questions in Intel Community.

I guess you're using SignalTap to check the signal at your end.

Can you provide some information regarding the issue such snapshots?

Is there any calibration failure occurred during the test?

Can you provide the DDR4 example design here?

Regards,

Adzim

[AdzimZM_Intel]

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.