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Arria 10 GX PCIe Dev Kit and the AvalonMM DMA design example

Altera_Forum
Honored Contributor II
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Hello, 

 

I'm struggling to adapt the AN690 design example for my own use, and I can't seem to be able to figure out what I'm doing wrong. While I'm fluent in HDL I'm new to Qsys, which I've been struggling with. Essentially all I'm trying to do is change the design from defining a simple RAM in Qsys to use as on-chip memory, to providing myself HDL access to the Avalon-MM slave interfaces directly. This way I can provide my own behavior instead of only the built-in RAM IP. At first I just need basic interfacing like register reads/writes, but I need to be able to scale it to a high-throughput application, which is why the DMA example was attractive. 

 

I was able to get the unmodified AN690 working just fine. I created a generic component with similar interfacing to the "On-Chip Memory" block I'm replacing, and put very basic Avalon-MM slave logic inside. 

 

I've loaded the design and it shows up on the bus. However, as soon as I attempt a read or write, the host OS (Ubuntu 16.04) locks up hard (no kernel panic, still producing video, but completely unresponsive). I suspect it's not responding, or not responding correctly, to a PCIe transaction causing the bus to lock up, but I'm not sure. Any ideas what I'm doing wrong, or how to diagnose? 

 

I've attached a QAR of the project in question, and a jpeg of the original Qsys connections (for comparison). It's basically AN690 with the above modifications. 

 

Thanks!
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