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Arria 10 HPS DDR4 calibration fail and no emif_usr_clk

User1580871742356367
334 Views

Story:

  1. HPS DDR4 calibration failed (discrete, 32bit).
  2. No emif_usr_clk by putting signal tap
  3. PLL locked
  4. both local_cal_success and local_cal_fail are LOW  

 

Questions:

  1. Why there was no emif_usr_clk?
  2. Was Calibration requires SW (boot code/uboot or so)?
0 Kudos
6 Replies
sstrell
Honored Contributor III
330 Views

What leads to you believing there is no emif_usr_clk? Do you not see it coming from the IP in Platform Designer?

 

And the first stage bootloader is what runs to initialize and calibrate the external memory, so this is before uboot for Arria 10.

 

#iwork4intel

User1580871742356367
322 Views

Thank you very much for the reply.

emif_usr_clk is used as Signal Tap clock and Signal Tap was triggering and waiting for the clock.

ybin
Employee
326 Views
Agree with sstrell’s opinion. If the PLL is locked, the emif_usr_clk should be OK. Please make sure you tap the correct signal in signaltap. The calibration should act before uboot. As A10 HPS EMIF can be test separately, I think you can use an example design to test EMIF, to see if EMIF can calibrate seperately. Please refer to below link for how to https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20118.pdf
User1580871742356367
318 Views

The fitter was failed if using HPS EMIF DDR4 pins (same as A10 SOC Eval Kit) when generating FPGA EMIF example design. 

Alert_n pin is on AG24 and the pins are working for HPS EMIF ( GHRD NAND design)

Have played with Alert_n settings etc. in Parameters (DQS group, Addr/CMD or auto) and no luck. 

Any suggestions?

 

 

ybin
Employee
314 Views

You need to check whether all the pin location assignment and IP parameter is the same as GHRD . 

ybin_1-1593317557704.png

 

 

 

ybin
Employee
282 Views

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