What leads to you believing there is no emif_usr_clk? Do you not see it coming from the IP in Platform Designer?
And the first stage bootloader is what runs to initialize and calibrate the external memory, so this is before uboot for Arria 10.
The fitter was failed if using HPS EMIF DDR4 pins (same as A10 SOC Eval Kit) when generating FPGA EMIF example design.
Alert_n pin is on AG24 and the pins are working for HPS EMIF ( GHRD NAND design)
Have played with Alert_n settings etc. in Parameters (DQS group, Addr/CMD or auto) and no luck.
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