FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
4965 Discussions

Arria 10 : HPS to FPGA Bridge Enable

PJais1
Novice
527 Views

Hello,

 

I am using Arria 10 SoC on custom board and want to design a program for HPS and FPGA communication. In the manuals I read that we need to enable the bridges for HPS and FPGA communication .

I have generated dtb file using sopc2dts tool and used the board info xml files.

The linux dts file includes the bridges address but no bridge enable command is included:

 

sopc0: sopc@0 {

device_type = "soc";

ranges;

#address-cells = <1>;

#size-cells = <1>;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = <0>;

 

a10_hps_bridges: bridge@0xc0000000 {

compatible = "altr,bridge-17.1", "simple-bus";

reg = <0xc0000000 0x20000000>,

<0xff200000 0x00200000>;

reg-names = "axi_h2f", "axi_h2f_lw";

clocks = <&clk_0 &clk_0 &clk_0 &clk_0>;

clock-names = "h2f_axi_clock", "h2f_lw_axi_clock", "f2sdram0_clock", "f2sdram2_clock";

#address-cells = <2>;

#size-cells = <1>;

ranges = <0x00000000 0x00040000 0xc0040000 0x00000004>,

<0x00000000 0x00040004 0xc0040004 0x00000004>,

<0x00000000 0x00000000 0xc0000000 0x00040000>,

<0x00000001 0x00000000 0xff200000 0x00000020>,

<0x00000001 0x00000020 0xff200020 0x00000020>,

<0x00000001 0x00000200 0xff200200 0x00000100>,

<0x00000001 0x00000330 0xff200330 0x00000008>,

<0x00000001 0x00000320 0xff200320 0x00000010>,

<0x00000001 0x00000310 0xff200310 0x00000010>,

<0x00000001 0x00000300 0xff200300 0x00000010>;

 

On booting , no message of bridge initialisation is printed on console output.

The commnad : dmesg | grep fpga prints following output-

                      

[  1.117432] socfpga-dwmac ff800000.ethernet: PTP uses main clock       

[  1.123676] socfpga-dwmac ff800000.ethernet: User ID: 0x10, Synopsys ID: 0x37

[  1.130827] socfpga-dwmac ff800000.ethernet:     DWMAC1000        

[  1.136046] socfpga-dwmac ff800000.ethernet: DMA HW capability register suppd

[  1.143497] socfpga-dwmac ff800000.ethernet: RX Checksum Offload Engine suppd

[  1.150957] socfpga-dwmac ff800000.ethernet: COE Type 2            

[  1.156170] socfpga-dwmac ff800000.ethernet: TX Checksum insertion supported 

[  1.163187] socfpga-dwmac ff800000.ethernet: Enhanced/Alternate descriptors  

[  1.170127] socfpga-dwmac ff800000.ethernet: Enabled extended descriptors   

[  1.176895] socfpga-dwmac ff800000.ethernet: Ring mode enabled        

[  1.182703] socfpga-dwmac ff800000.ethernet: Enable RX Mitigation via HW Watr

[  1.371423] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered    

[  2.907781] systemd[1]: Configuration file /lib/systemd/system/fpga-overlay..

[  6.566431] socfpga-dwmac ff800000.ethernet eth0: No Safety Features supportd

[  6.574028] socfpga-dwmac ff800000.ethernet eth0: IEEE 1588-2008 Advanced Tid

[  6.583696] socfpga-dwmac ff800000.ethernet eth0: registered PTP clock 

 

I need to enable the bridges also read and write some data from HPS to FPGA . I also tried to read and write over memory(addresses of bridges) using mw and md commands at uboot level . But there is data abort error and the commands are resetting the CPU .

 

Could anyone please help with the same.

 

Thanks ,

Priya

 

0 Kudos
3 Replies
EBERLAZARE_I_Intel
323 Views

Hi,

 

Can I get the Quartus and SoC EDS version that you are using?

 

Were you able to enable this using the Arria 10 SoC dev-kit?

 

I apologize for the delay in response.

PJais1
Novice
323 Views

Hello @EberL_Intel​ ,

 

I am using Quartus Prime Pro v17.1 and SoC EDS v17.1 . No, i am not using arria 10 development kit ,all the testing is done on custom board.

I did some changes in the dts file itself, by taking reference from some previous forum answers.

Now the bridges are displayed using dmesg | grep command , but a different error is encountered.

 

root@arria10:~# dmesg | grep fpga

[  1.077679] socfpga-dwmac ff800000.ethernet: PTP uses main clock

[  1.083888] socfpga-dwmac ff800000.ethernet: User ID: 0x10, Synopsys ID: 0x37

[  1.091023] socfpga-dwmac ff800000.ethernet:     DWMAC1000

[  1.096238] socfpga-dwmac ff800000.ethernet: DMA HW capability register supported

[  1.103688] socfpga-dwmac ff800000.ethernet: RX Checksum Offload Engine supported

[  1.111147] socfpga-dwmac ff800000.ethernet: COE Type 2

[  1.116356] socfpga-dwmac ff800000.ethernet: TX Checksum insertion supported

[  1.123373] socfpga-dwmac ff800000.ethernet: Enhanced/Alternate descriptors

[  1.130318] socfpga-dwmac ff800000.ethernet: Enabled extended descriptors

[  1.137084] socfpga-dwmac ff800000.ethernet: Ring mode enabled

[  1.142893] socfpga-dwmac ff800000.ethernet: Enable RX Mitigation via HW Watchdog Timer

[  1.331499] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered

[  1.338379] altera_hps2fpga_bridge c0000000.fpgabridge: regmap for altr,l3regs lookup failed

[  1.346926] altera_hps2fpga_bridge ff200000.fpgabridge: regmap for altr,l3regs lookup failed

[  2.623801] systemd[1]: Configuration file /lib/systemd/system/fpga-overlay.service is marked executable. Please remove executable permissio.

[  8.191159] socfpga-dwmac ff800000.ethernet eth0: No Safety Features support found

[  8.198759] socfpga-dwmac ff800000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported

[  8.207705] socfpga-dwmac ff800000.ethernet eth0: registered PTP clock

 

Can you help with the above error.

 

Thanks,

Priya

 

EBERLAZARE_I_Intel
323 Views

Hi Priya,

 

I am still working on this issue, as this was tested for a custom board, there are a lot of factors that might be affecting.

 

I will check with our internal team and try to find if there are any similar cases.

 

Regards.

Reply