Arria 10 SX 10Gbase Avalon FIFO HPS Driver

[Joshua_Willson]

I am trying to implement the Arria 10 SOC Scalable Multispeed 10M-10G
Ethernet Design.  However instead of using a loopback testing system I want to implement the testing with the HPS and network manager. I found the Stratix 10 SOC Design Example for 10Gbe on rocketboards and they have a design example with the HPS. This design uses DMA to send packets between the HPS and  the LL 10GB MAC. For the Arria 10 design I want to use the Avalon ST single clock FIFO. I do not know how to interact with this FIFO. I cant not find the supported linux drivers to interact with this IP.  Any help would be great. Thanks. 

[EricMunYew_C_Intel]

You can refer to below for building bootloader and generating the Linux kernel.

https://rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10

[EricMunYew_C_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.