I am trying to determine if a certain FMC ADC board is compatible with a 3rd party Arria 10 SX FMC carrier card, transceiver speed grade 2, fpga fabric speed grade -1. The ADC board has 4 source synchronous serial LVDS interfaces, so 4 clock pairs and 4 data pairs. The serial clock rate is 600 MHz. Unfortunately the clocks are not being routed to any of the regional clock capable pins (*_CC) of the Arria 10. The Arria 10 handbook seems to indicate that you can promote a non-dedicated clock pin to a global clock:
"Intel recommends providing the I/O PLL reference clock using a dedicated pin when possible. If you want to use a non-dedicated pin for the PLL reference clock, you have to explicitly promote the clock to a global signal in the Intel Quartus Prime software. "
Does this mean it is possible to operate the LVDS SERDES using the ADC clocks, promoted to a global pin?
Could this method work, or is there a different way to interface with this serial stream?
I would strongly recommend to use a dedicated clock pin , if you are using Altera LVDS IP , other wise you may encounter some fitter issues when using Altera LVDS IP.
The boards are already designed so I can't move the pins. If I promote the pin to a global clock, use that for the SERDES, and the design still meets timing, will it work or not?