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Beginner
234 Views

Arria 10 SX LVDS SERDES with global clocks?

I am trying to determine if a certain FMC ADC board is compatible with a 3rd party Arria 10 SX FMC carrier card, transceiver speed grade 2, fpga fabric speed grade -1. The ADC board has 4 source synchronous serial LVDS interfaces, so 4 clock pairs and 4 data pairs. The serial clock rate is 600 MHz. Unfortunately the clocks are not being routed to any of the regional clock capable pins (*_CC) of the Arria 10. The Arria 10 handbook seems to indicate that you can promote a non-dedicated clock pin to a global clock:

 

"Intel recommends providing the I/O PLL reference clock using a dedicated pin when possible. If you want to use a non-dedicated pin for the PLL reference clock, you have to explicitly promote the clock to a global signal in the Intel Quartus Prime software. "

 

Does this mean it is possible to operate the LVDS SERDES using the ADC clocks, promoted to a global pin?

 

Could this method work, or is there a different way to interface with this serial stream?

 

 

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9 Replies
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Employee
6 Views

Hi,

I would strongly recommend to use a dedicated clock pin , if you are using Altera LVDS IP , other wise you may encounter some fitter issues when using Altera LVDS IP.

 

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Beginner
6 Views

The boards are already designed so I can't move the pins. If I promote the pin to a global clock, use that for the SERDES, and the design still meets timing, will it work or not?

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Employee
6 Views

Hi,

Hope the issue is resolved with solution provided in the private message

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Beginner
6 Views

I have not seen a private message related to this issue. Can you resend?

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Employee
6 Views

Hi ,

Can you please check again.

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Employee
6 Views

Hi ,

Kindly let me know your updated status .

 

Regards,

Rahul S

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Beginner
6 Views

Yes, thank you I have now received the private message. I will try what you suggest.

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Employee
6 Views

Thanks for the acknowledgement

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Employee
6 Views

Hi ,

 

 Kindly let me know, if you need further assistance.

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