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PHJ
New Contributor I
1,765 Views

Arria 10 SoC DevKit: Can I drive DB-9 RS-232 port from HPS UART0 ?

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The user guide indicates that this is available after FPGA configuration.

What needs to be configured for this to work ?

​Does the GSRD support this ?

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1 Solution
PHJ
New Contributor I
248 Views

 

​Hi,

 

I now have the HPS UART0 routed through the FPGA OK to the DB9 RS-232 port. 

The UART_RS232 soft IP is not required in the FPGA. 

My problem here was caused by the RS-232 PHY on the dev board operating in an auto-shutdown mode that meant that the external tx/rx loopback test I was attempting would never wake the PHY.

 

Thanks,

 

Paul

View solution in original post

8 Replies
Ahmed_H_Intel1
Employee
248 Views

Hi,

The RS-232 component on the board can be accessed by the "UART_RS-232 soft IP" in the platform designer (Qsys). So what you need is to connect the HPS IP to RS232 IP in the platform designer.

Also you still can use the NIOS II to control the RS232 and send the data to HPS in case of using the NIOS II as a master core.

 

Please refer to the UART core description in the following page:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=...

 

Regards.

PHJ
New Contributor I
248 Views

Hi -

 

Sorry - been off working on other things for a while....

I'm confused here.....Why would I need the "UART_RS-232 soft IP" ? The UART controller is already implemented as UART0 in the HPS isn't it ?  Can I not just get the HPS UART0 Rx/Tx signals routed to CRC_ERROR (AU21)/CVP_CONFDONE(AV22) in the FPGA without adding the FPGA UART soft IP ?  If so, are there some simple steps for a platform designer novice to follow to do this or an example design that does this available ?

 

Thanks !

PHJ
New Contributor I
248 Views

​Can someone from Intel please comment on this ?

I need to receive/transmit data from/to the dev board DB-9 RS-232 port on UART0 in the HPS. 

What FPGA configuration do I need for  this - do I need the UART_RS-232 soft IP implemented in the FPGA, or can I just configure the HPS UART0 Rx/Tx signals to be routed to CRC_ERROR/CVP_CONFDONE ?

Is any configuration required in the MAX V for this ?

Ahmed_H_Intel1
Employee
248 Views

Hi,

I will check what configuration you need and will let you know shortly.

PHJ
New Contributor I
249 Views

 

​Hi,

 

I now have the HPS UART0 routed through the FPGA OK to the DB9 RS-232 port. 

The UART_RS232 soft IP is not required in the FPGA. 

My problem here was caused by the RS-232 PHY on the dev board operating in an auto-shutdown mode that meant that the external tx/rx loopback test I was attempting would never wake the PHY.

 

Thanks,

 

Paul

View solution in original post

GSagl1
Novice
248 Views

Hi,

 

How did you do this? What is FPGA OK? I have a design in my FPGA and I'm not using the HPS at all, and I want to use UART to send data to the design in the FPGA. Is this what you also did, and How?

 

I hope you can help me understand what's going on,

 

Gurol

PHJ
New Contributor I
248 Views

​Hi Gurol -

 

We configured the pinmux in the HPS to route UART0 via the FPGA:

 

/* UART0 routed via FPGA */

alt_write_word(ALT_PINMUX_FPGA_UART0_USEFPGA_ADDR, ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET(1));

 

We  configured the FPGA to route the HPS UART0 signals to the appropriate input/output pins of the A10 - we only used tx/rx as we were not using flow control.

 

Best Regards,

 

Paul

 

 

 

 

 

 

 

corestar
New Contributor I
201 Views

Hello, I'm having a similar problem except I want to access the RS-232 via the DB-9 on J25. I see the TX line togging coming out of the FPGA but nothing shows up on the Teraterm on the PC. Works fine with JTAG UART, but that little window in the NIOS-II tools is really annoying.

Can you explain how you fixed the auto shutdown issue on the RS-232 Phy?

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