FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Arria 10 SoC Development Kit FPGA Memory Interface

Honored Contributor II

I am using Arria 10 SoC Development Kit right now and trying to get access to the FPGA memory. 


What I have done is generating the EMIF IP with preset ( Arria 10 SoC Development Kit FPGA Memory 72x) together with the Avalon bus DDR test verilog code. 

But still cannot read from DDR4. Here I posted the captured waveform from signaltap. Is there anyone could help? 

The name of each signal is quite obvious 


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