Arria 10 : data abort after DDR calibration

[PJais1]

Hello,

I am designing Linux OS for our custom board based on Arria 10 SoC.I have build uboot and peripheral rbf image and uploaded them in SD card.In our custom board we have used DDR3 memory at HPS side.

While booting, the console is showing a data abort and prefetch error after DDR calibration:

U-Boot 2014.10 (Sep 19 2019 - 11:13:27)

CPU  : Altera SOCFPGA Arria 10 Platform

BOARD : Altera SOCFPGA Arria 10 Dev Kit

I2C:  ready

DRAM: WARNING: Caches not enabled

FPGA: writing ghrd_10as066n2.periph.rbf..

FPGA: Early Release Succeeded.

SF: Detected N25Q1024A with page size 256 Bytes, erase size 4 KiB, total 128 MiB

DDRCAL: Success

INFO : Skip relocation as SDRAM is non secure memory

Reserving 2048 Bytes for IRQ stack at: ffe3a6e8

DRAM : 2 GiB

Wdata abort

prefetch aààort

Could anyone please suggest how to remove this error?

Thanks,

Priya

[EBERLAZARE_I_Intel]

Hi,

Just to check, when using the DDR4 memory, were you able to boot the Arria 10 successfully?

Are you using the design from our GHRD?

Regards.

[PJais1]

Hello,

I haven't designed using DDR4 as in our custom design DDR3 is connected at HPS side. Also , I am using the design from example design in SOC EDS embedded folder .

[EBERLAZARE_I_Intel]

Hi,

I've noticed you are using Early IO release feature. This means there should be two .rbf files needed, peripheral and core.

[EBERLAZARE_I_Intel]

I recommend that you refer the user guide to use Early IO release feature:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-fpga-early-io-release.pdf

Regards.

[PJais1]

Hello ,

I have followed the same manual for early release IO and created peripheral and core rbf and specified peripheral in bsp-editor. In the sd card , i have loaded both core and peripheral rbf.

Also, I have tried full configuration feature, where i loaded a single rbf and removed early IO feature.The uboot hangs after DDR calibration.

As I searched in the uboot source code, the misc.c file in arch/arm/cpu/armv7/socfpga_arria10 , the code hangs at below line in the skip_relocation() function:

/* assign the global data to new location, no longer in stack */

gd = id;

/* rebase the stack pointer as we won’t jump back here */

asm volatile (“mov sp, %0” : : “r” (gd->start_addr_sp)

: “r0”, “r1”, “r2”, “r3”, “ip”, “lr”, “memory”, “cc”);

Could you please help with above issue?

[R_]

Hi,

I am also getting same error.Did you solve the issue.

[R_]

Can provide some inputs regarding this?

[PJais1]

Hello,

As we have replaced DDR4 with DDR3 , we have updated all the timing parameters, using the datasheet of MT41K512M16HA-107(DDR3) in our memory timing i/o in quartus tool and successfully booted U-boot.

If you are having same data abort error after callibration, check all the timing and speed parameters according to the DDR which you have used.

Thanks.

[R_]

We have 2GB DDR4 memory with ECC enabled and some of the boot times we are getting below error

U-Boot 2014.10 (Sep 25 2019 - 16:32:41)

CPU  : Altera SOCFPGA Arria 10 Platform

BOARD : Altera SOCFPGA Arria 10

I2C:  ready

DRAM: WARNING: Caches not enabled

SOCFPGA DWMMC: 0

FPGA: writing ghrd_10as066n2.periph.rbf ...

FPGA: Early Release Succeeded.

DDRCAL: Success

SDRAM: Initializing ECC 0x00000000 - 0x80000000

SDRAM-ECC: Initialized success with 2148 ms

INFO : Skip relocation as SDRAM is non secure memory

Reserving 2048 Bytes for IRQ stack at: ffe386e8

DRAM : 2 GiB

Error: DRAM address mismatch error occurred

decoder0: erraddr = 7fefefc0

decoder1: erraddr = 7fefefc0

decoder2: erraddr = 7fefefc0

decoder3: erraddr = 7fefefc0

### ERROR ### Please RESET the board ###

Error: DRAM ECC DBE occurred

erraddr = 7fefefe0

### ERROR ### Please RESET the board ###

Info: DRAM ECC SBE @ 0x7fefefc0

Info: DRAM ECC AUTO CORRECTION SBE ADDRESS @ 0x7fefefc0

decoder0: erraddr = 7fefefc0

decoder1: erraddr = 7fefefc0

decoder2: erraddr = 7fefefc0

decoder3: erraddr = 7fefefc0

When i check source code of uboot it is failing with below line

/* rebase the stack pointer as we won’t jump back here */

asm volatile (“mov sp, %0” : : “r” (gd->start_addr_sp)

: “r0”, “r1”, “r2”, “r3”, “ip”, “lr”, “memory”, “cc”);

Do you have any idea?

Regards

[Jay_Foresys]

R_ 

Did you determine the cause/resolution of the error:  Error: DRAM ECC DBE occurred ?

[PJais1]

Hello,

In our design we did not had ECC enabled . You might check the design parameters in the quartus tool for the DDR used.