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Arria 10 hold violations

IanD
Novice
876 Views

Hello,

Using an Arria 10 board. Setup timing is clean, but I'm getting a few hold violations from the Arria PHY to an input FIFO. Clocks are correct and the violation only shows up sometimes. I.E - when signaltap is used.

Any ideas on how I can fix these? Is there a post-route option or pre-route constraint?

 

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RichardTanSY_Intel
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Do you mean the hold violation occur sometimes? Do you get it to pass timing before?

If so, it might be marginal issue. Try to run seed sweep to get the best fit that close timing.


Do you have enough positive slack for setup? You can set "All paths" in the "Optimize Hold Timing" in the Advanced Fitter setting in the Compiler Setting.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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IanD
Novice
847 Views

Thanks Richard. This only happens sometimes. The problem flop-flop paths have plenty of setup, but other paths on the same clock are just meeting setup.

I do have the "Optimize Hold timing" set, but I would like to try the seed sweep when I next see the problem. I don't see this option in version 21.3. Where can I find it?

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RichardTanSY_Intel
831 Views

You may checkout this video on how to run seed sweep.

https://www.youtube.com/watch?v=1cc74E3zaeI


Best Regards,

Richard Tan


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RichardTanSY_Intel
779 Views

Hi, do you need further help in regards to this case?


Best Regards,

Richard Tan


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RichardTanSY_Intel
746 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support.

 

Best Regards,

Richard Tan


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