Is there are possibility to design the PCB with the Arria10 in such way that it is possible to shutdown the FPGA part while keeping the HPS running and being able to communicate with the HPS via Ethernet. The purpose is to avoid overheating of the system while being able to explore and configure the device for further use in optimal thermal conditions.
In https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-device-design-guidelines.pdf, section 126.96.36.199 Managing Power by Shutting Down Supplies it is written that shutting down VCC will affect I/Os. But is there any solutions to my task?
For the HPS to be fully operational, the FPGA supply voltages monitored by the POR circuitry must be above their POR values. HPS is a Hard IP reside in FPGA and it needs to use the Periphery of FPGA to work.
There are options to clock gate the FPGA Fabric when they are not in use to reduce power which you can explore on this approach.