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Arria II GX Dev Kit - Ethernet RGMII

Altera_Forum
Honored Contributor II
‎06-24-2011 02:35 PM
909 Views

Hi  

 

I am new to FPGA world and thanks for the time.  

 

I am trying to run following reference design in lookback mode. 

 

http://www.alterawiki.com/wiki/triple_speed_ethernet_with_rgmii_interface_hardware_test_by_using_system_console_reference_design 

 

Some how what ever I do I am not able to see any packets transmitted. I feel I am making very silly mistake.  

 

If I load default Web-Server I can see Tx LED flashing indicating packet transmission. So there is no hardware issues.  

 

Thanks for the help in advance.
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Altera_Forum
Honored Contributor II
‎06-24-2011 09:40 PM
218 Views

Load the sample project and copy tse_my_system.c file to Your project.

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Altera_Forum
Honored Contributor II
‎06-27-2011 05:12 PM
218 Views

I am using Quartus 10 sp1.  

I found the issue. There is a clock shift for Tx_clk and Rx_Clk in PHY.  

I changed the Clock to 90 degree shift and every thing is working fine.  

 

Thanks for the help.
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