FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5238 Discussions

Arria II GX Dev Kit - Ethernet RGMII

Altera_Forum
Honored Contributor II
784 Views

Hi  

 

I am new to FPGA world and thanks for the time.  

 

I am trying to run following reference design in lookback mode. 

 

http://www.alterawiki.com/wiki/triple_speed_ethernet_with_rgmii_interface_hardware_test_by_using_sys... 

 

Some how what ever I do I am not able to see any packets transmitted. I feel I am making very silly mistake.  

 

If I load default Web-Server I can see Tx LED flashing indicating packet transmission. So there is no hardware issues.  

 

Thanks for the help in advance.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
93 Views

Load the sample project and copy tse_my_system.c file to Your project.

Altera_Forum
Honored Contributor II
93 Views

I am using Quartus 10 sp1.  

I found the issue. There is a clock shift for Tx_clk and Rx_Clk in PHY.  

I changed the Clock to 90 degree shift and every thing is working fine.  

 

Thanks for the help.
Reply