HiI am new to FPGA world and thanks for the time. I am trying to run following reference design in lookback mode. http://www.alterawiki.com/wiki/triple_speed_ethernet_with_rgmii_interface_hardware_test_by_using_sys... Some how what ever I do I am not able to see any packets transmitted. I feel I am making very silly mistake. If I load default Web-Server I can see Tx LED flashing indicating packet transmission. So there is no hardware issues. Thanks for the help in advance.
I am using Quartus 10 sp1.I found the issue. There is a clock shift for Tx_clk and Rx_Clk in PHY. I changed the Clock to 90 degree shift and every thing is working fine. Thanks for the help.