07-17-2015 04:29 PM
I am working with the web server project and am having problems with the on board PHY. The board seems to be stuck on the PHY reset.I went through the steps to reload the FLASH from factory recovery using the steps outlined in the user guide and version 184.108.40.206 to see if this would help with the communication issues: 1) Write a5gx_starter_fpga_bup_top.sof to the FPGA 2) Open the NIOS command shell and run ./restore.sh which loads the file a5gx_starter_fpga_bup_hw.flash into flash memory. 3) Toggle power on the board. 4) Reload the a5gx_starter_fpga_bup_top.sof into the FPGA 5) Launch the nios2-terminal program The output from the NOIS2- terminal is shown below: PHY INFO: [phyid] 0x0 141 c2 PHY INFO: Issuing PHY Reset PHY INFO: waiting on PHY link.. I did read about the MAC address being reset but it doesn't prompt me to update it so not sure if this is the problem or if there is a problem with the hardware on my board. Any help would be appreciated. -KIM
07-18-2015 01:45 AM
Hi Kim,Just wonder which specific PHY is referred in the above? Is it the Altera transceiver PHY IP? If yes, probably you could further check if the reference clock frequency and the mgmt_clk frequency are of correct frequency.
07-18-2015 09:07 PM
Hi Tiny,The PHY is the Marvel 88E1111. It is connected to the MAC in RGMII mode. The enet_gtx_clk signal is connected to a ddio_buffer to handle the high speed interface. It is fed by the tx_clk_to_the_tse_mac which is selected by the current mode of the MAC which can be the GbE mode at 125MHz, the 100Mb mode which is 25Mhz, or the 10 Mb mode which is 2.5MHz. I opened the project file in Quartus v12.1sp1 and built it so that I could generate the RTL which is attached. This is all default from the development board kit. - Kim