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JOter
Beginner
422 Views

Arria V - Q18- Time quest. We have some kind of problems using "set_output_delay" command. We are using Q18 and Q18.1.

Though the time quest analyzer seems to OK, the physical output signal, measured in one scope, is not OK.

 

In both cases, We have implemented a basic Project with a clock and a counter. We have connected one counter bit to an external PCB pin. We have meassured in the scope the phase between both signal. We change the constraints file for differentes delays.

The configuration in Q 91. and CIII it seems to be OK, but in Q18.0 or Q18.1 and Arria V not.

We attach the Project.

Please, can tell us ig we are making something wrong or give us an idea about the way to resolve the problem?.

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4 Replies
47 Views

Hi JOter,

 

In the design, the output delay is set to only OUTPUT[0]. May I know what are the both signals mentioned? What is the signals that are not ok as there is no violation in the design?

 

Thanks.

 

JOter
Beginner
47 Views

Hi,

 

Thank you for your answer. I didn't see it until now, because a was waiting it in the support panel instead of "Comunity" panel.

 

In reference to your question the signal are: RAM_CLK (CLK) and OUTPUT 0 (counter)

We tested both signal in one scope, and we didn't notice any change between them changing the OUTPUT_DELAY constraints.

Remenber we checked it also using a C III, and in this case we got the spected signal.

 

We used the next constrains commands:

set_output_delay -clock vt_RAM_CLK -max [expr $RAM_tsetup + $RAM_BDb_max - $RAM_CLK_DLY_MIN] [get_ports {OUTPUT[0]}]

set_output_delay -clock vt_RAM_CLK -min [expr -$RAM_thold + $RAM_BDb_min - $RAM_CLK_DLY_MAX] [get_ports {OUTPUT[0]}]

 

And

set_output_delay -clock RAM_CLK -max [expr $RAM_tsetup + $RAM_BDb_max - $RAM_CLK_DLY_MIN] [get_ports {OUTPUT[0]}]

set_output_delay -clock RAM_CLK -min [expr -$RAM_thold + $RAM_BDb_min - $RAM_CLK_DLY_MAX] [get_ports {OUTPUT[0]}]

 

Best regards

 

47 Views

Hi JOter, Any updates? Thanks
GuaBin_N_Intel
Employee
47 Views

In your design, the signal "OUTPUT[0]" is fix to IO register (refer to Fitter report>Resource Section>Output Pins>Output Register) which means only IO delay chain option can adjust the delay to external pin. So, I dont think it will change if the delay is set to zero (fastest route) even you change your output constraint.
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