Arria V Soc Development Kit - getting started

[Altera_Forum]

We have several brand new Arria V SoC Development Kits from Arrow. 

 The switches and jumpers are set as per the June 2014 Arriva V SoC Development kit guide.  The board boots to Hello Tim! and fetches an IP address from a DHCP. We can access the board's web page from a PC on the same DHCP network.  However we have some problems ...  1) When we power a board up, it does not light the Config Done LED (D38) as described in the Development kit guide.  2) The board's web page says that the FPGA is not loaded  2) The Board Test System connects, but does not display MAC addresses etc, the System info and GPIO tabs are disabled. The Messages box says "Connecting to the target... java.lang.Exception: No BoardTestSystem-compatible design exists in the FPGA. Please select a design from the configure menu."  4) The Configure menu and then dailogue for GPIO load looks to run to completion but still the GPIO tab is disabled.  If someone could help us get the kits going, that would be great.   Thanks,  Bill Chadwick Thales Research UK

[Altera_Forum]

boot log includes the following ... 

 reading u-boot.scr 200 bytes read in 6 ms (32.2 KiB/s) # # Executing script at 02000000 reading soc_system.rbf 6840534 bytes read in 2351 ms (2.8 MiB/s) altera_load: Failed with error code -4 fpgaintf ffd08028: 00000000 .... fpga2sdram ffc25080: 00000111 .... axibridge ffd0501c: 00000000 .... reading zImage 3202824 bytes read in 1101 ms (2.8 MiB/s) reading socfpga.dtb 18025 bytes read in 15 ms (1.1 MiB/s) # # Flattened Device Tree blob at 00000100  Booting using the fdt blob at 0x00000100  Loading Device Tree to 03ff8000, end 03fff668 ... OK

[Altera_Forum]

Hi bChadwick, 

 Are you already resolved the issues?, I'm experiencing same issue with setting up the board.  Thanks,  Alex.

[Altera_Forum]

Alex, 

 I think our board was shipped with none/wrong FPGA firmware.  The instructions for reloading the 'factory' data were badly flawed (I have not checked to see if they have been updated).  In the end I spent 1/2 an hour on the phone with a chap from Altera as we went through reprogramming the board.   After that it worked for a while but eventually the FPGA stopped loading at boot time again. We had done our eval by then so did not bother resurrecting it.  Also the v 14.0 Linux SD card image did not work on our board. We stuck with 13.1 (the last version to support Win XP).  All in all, a rather disappointing experience.

[Altera_Forum]

Hi bChadwick, 

 I'd supposed same reason with the board factory settings, one question your Board Test System is working? I'm still trying to Setting Up the Board Restoring the MAX V CPLD and CFI Flash Device but at the moment to try restore the CFI Flash it is neccesary Select the flash image .pof file: <install  dir>\kits\arriaVST_5astfd5kf40es_soc\factory_recovery\output_file.pof. but this image file doesn't exist. I'm disappointed, but my research depends of fix that.

[Altera_Forum]

--- Quote Start ---  boot log includes the following ...  reading u-boot.scr 200 bytes read in 6 ms (32.2 KiB/s)# # Executing script at 02000000 reading soc_system.rbf 6840534 bytes read in 2351 ms (2.8 MiB/s) altera_load: Failed with error code -4 fpgaintf ffd08028: 00000000 .... fpga2sdram ffc25080: 00000111 .... axibridge ffd0501c: 00000000 .... reading zImage 3202824 bytes read in 1101 ms (2.8 MiB/s) reading socfpga.dtb 18025 bytes read in 15 ms (1.1 MiB/s)# # Flattened Device Tree blob at 00000100  Booting using the fdt blob at 0x00000100  Loading Device Tree to 03ff8000, end 03fff668 ... OK  --- Quote End ---     hello, I met the problem altera_load: Failed with error code -4 as you do when I program fpga with FPPx8 mode, after I changed the mode to FPPx16, it worked well, hope this helps you